// **************************************************************
// COPYRIGHT(c)2020, Xidian University
// All rights reserved.
//
// IP LIB INDEX : 
// IP Name      : 
//                
// File name    : eth_mac_phy_x4.v
// Module name  : 
// Full name    :
//
// Author       :  Hbing 
// Email        :  2629029232@qq.com
// Data         :  2020/10/12
// Version      :  V 1.0 
// 
// Abstract      :  
// Called by    :  Father Module
// 
// Modification history
// ------------------------------------------------------------------------------------------------------
// 
//  
// *********************************************************************
// *******************
// DESCRIPTION
// *******************
//
// 
// 
// *******************
// DEFINE(s)
// *******************
`timescale 1ns/10fs
`include "common_header.verilog"
`include "dwc_e12mp_phy_x4_ns_pcs_raw_macros.v"

// *******************
// DEFINE MODULE PORT
module eth_mac_phy(
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
    rx0_cdr_ppm_max   ,
    rx1_cdr_ppm_max   ,
    rx2_cdr_ppm_max   ,
    rx3_cdr_ppm_max   ,

    rx0_ppm_drift     ,
    rx0_ppm_drift_vld ,
    rx1_ppm_drift     ,
    rx1_ppm_drift_vld ,
    rx2_ppm_drift     ,
    rx2_ppm_drift_vld ,
    rx3_ppm_drift     ,
    rx3_ppm_drift_vld ,
`endif

`ifdef DWC_E12MP_X4NS_PG_PINS
    vp,
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    vpdig,
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    vph,
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    vptx0,
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    vptx1,
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    vptx2,
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    vptx3,
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    vsscore_0,
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    vsscore_1,
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    vsscore_2,
`endif
`ifdef DWC_PMA_PADS_PWRSW
    ana_pwr_en,
`endif
`ifdef DWC_PMA_PADS_PWRSW
    ana_pwr_stable,
`endif
    atb_f_p,
    atb_s_m,
    atb_s_p,
    bs_acmode,
    bs_actest,
    bs_cdr,
    bs_ce,
    bs_rx_bigswing,
    bs_rx_init,
    bs_rx_level,
    bs_sdr,
    bs_tdi,
    bs_tdo,
    bs_tx_lowswing,
    bs_udr,
    cr_para_ack,
    cr_para_addr,
    cr_para_clk,
    cr_para_rd_data,
    cr_para_rd_en,
    cr_para_sel,
    cr_para_wr_data,
    cr_para_wr_en,
    dtb_out,
`ifdef DWC_E12MP_X4NS_PG_PINS
    gd,
`endif
    jtag_tck,
    jtag_tdi,
    jtag_tdo,
    jtag_tdo_en,
    jtag_tms,
    jtag_trst_n,
    
    pcs_pwr_stable,
    pg_mode_en,
    pg_reset,
    pma_pwr_stable,
    pcs_pwr_en,
    pma_pwr_en,

    ref_pad_clk_m,
    ref_pad_clk_p,
    ref_repeat_clk_en,
    ref_repeat_clk_m,
    ref_repeat_clk_p,
    phy_ref_dig_clk,
    phy_reset,
    ref_clk_en,
    ref_use_pad,
    ref_alt_clk_m,
    ref_alt_clk_p,
    ref_clk_req,
    rtune_req,
    rtune_ack,
    resref,
    
    res_ack_in,
    res_ack_out,
    res_req_in,
    res_req_out,

    lanex_rx2tx_par_lb_en,
    lanex_tx2rx_ser_lb_en,

    rx0_req,
    rx0_ack, 

    rx1_req,
    rx1_ack,

    rx2_req,
    rx2_ack,

    rx3_req,
    rx3_ack,

    rx0_m,
    rx0_p,
    rx0_reset,
    
    rx1_m,
    rx1_p,
    rx1_reset,
    
    rx2_m,
    rx2_p,
    rx2_reset,
    
    rx3_m,
    rx3_p,
    rx3_reset,
    scan_cr_clk,
    scan_cr_in,
    scan_cr_out,
    scan_mode,
    scan_mplla_div16p5_clk,
    scan_mplla_div16p5_in,
    scan_mplla_div16p5_out,
    scan_mplla_div33_clk,
    scan_mplla_div66_clk,
    scan_mplla_div_clk,
    scan_mplla_div_in,
    scan_mplla_div_out,
    scan_mplla_dword_clk,
    scan_mplla_dword_in,
    scan_mplla_dword_out,
    scan_mplla_fb_clk,
    scan_mplla_fb_in,
    scan_mplla_fb_out,
    scan_mplla_oword_clk,
    scan_mplla_qword_clk,
    scan_mplla_qword_in,
    scan_mplla_qword_out,
    scan_mplla_ref_clk,
    scan_mplla_ref_in,
    scan_mplla_ref_out,
    scan_mplla_ssc_clk,
    scan_mplla_ssc_in,
    scan_mplla_ssc_out,
    scan_mplla_word_clk,
    scan_mplla_word_in,
    scan_mplla_word_out,
    scan_mpllb_div_clk,
    scan_mpllb_div_in,
    scan_mpllb_div_out,
    scan_mpllb_dword_clk,
    scan_mpllb_dword_in,
    scan_mpllb_dword_out,
    scan_mpllb_fb_clk,
    scan_mpllb_fb_in,
    scan_mpllb_fb_out,
    scan_mpllb_oword_clk,
    scan_mpllb_qword_clk,
    scan_mpllb_qword_in,
    scan_mpllb_qword_out,
    scan_mpllb_ref_clk,
    scan_mpllb_ref_in,
    scan_mpllb_ref_out,
    scan_mpllb_ssc_clk,
    scan_mpllb_ssc_in,
    scan_mpllb_ssc_out,
    scan_mpllb_word_clk,
    scan_mpllb_word_in,
    scan_mpllb_word_out,
    scan_ref_clk,
    scan_ref_dig_clk,
    scan_ref_dig_in,
    scan_ref_dig_out,
    scan_ref_in,
    scan_ref_out,
    scan_ref_range_clk,
    scan_ref_range_in,
    scan_ref_range_out,
    scan_rx0_adpt_clk,
    scan_rx0_adpt_in,
    scan_rx0_adpt_out,
    scan_rx0_asic_clk,
    scan_rx0_asic_in,
    scan_rx0_asic_out,
    scan_rx0_div16p5_clk,
    scan_rx0_div16p5_in,
    scan_rx0_div16p5_out,
    scan_rx0_dpll_clk,
    scan_rx0_dpll_in,
    scan_rx0_dpll_out,
    scan_rx0_dword_clk,
    scan_rx0_dword_in,
    scan_rx0_dword_out,
    scan_rx0_scope_clk,
    scan_rx0_scope_in,
    scan_rx0_scope_out,
    scan_rx0_stat_clk,
    scan_rx0_stat_in,
    scan_rx0_stat_out,
    scan_rx0_word_clk,
    scan_rx0_word_in,
    scan_rx0_word_out,
    scan_rx1_adpt_clk,
    scan_rx1_adpt_in,
    scan_rx1_adpt_out,
    scan_rx1_asic_clk,
    scan_rx1_asic_in,
    scan_rx1_asic_out,
    scan_rx1_div16p5_clk,
    scan_rx1_div16p5_in,
    scan_rx1_div16p5_out,
    scan_rx1_dpll_clk,
    scan_rx1_dpll_in,
    scan_rx1_dpll_out,
    scan_rx1_dword_clk,
    scan_rx1_dword_in,
    scan_rx1_dword_out,
    scan_rx1_scope_clk,
    scan_rx1_scope_in,
    scan_rx1_scope_out,
    scan_rx1_stat_clk,
    scan_rx1_stat_in,
    scan_rx1_stat_out,
    scan_rx1_word_clk,
    scan_rx1_word_in,
    scan_rx1_word_out,
    scan_rx2_adpt_clk,
    scan_rx2_adpt_in,
    scan_rx2_adpt_out,
    scan_rx2_asic_clk,
    scan_rx2_asic_in,
    scan_rx2_asic_out,
    scan_rx2_div16p5_clk,
    scan_rx2_div16p5_in,
    scan_rx2_div16p5_out,
    scan_rx2_dpll_clk,
    scan_rx2_dpll_in,
    scan_rx2_dpll_out,
    scan_rx2_dword_clk,
    scan_rx2_dword_in,
    scan_rx2_dword_out,
    scan_rx2_scope_clk,
    scan_rx2_scope_in,
    scan_rx2_scope_out,
    scan_rx2_stat_clk,
    scan_rx2_stat_in,
    scan_rx2_stat_out,
    scan_rx2_word_clk,
    scan_rx2_word_in,
    scan_rx2_word_out,
    scan_rx3_adpt_clk,
    scan_rx3_adpt_in,
    scan_rx3_adpt_out,
    scan_rx3_asic_clk,
    scan_rx3_asic_in,
    scan_rx3_asic_out,
    scan_rx3_div16p5_clk,
    scan_rx3_div16p5_in,
    scan_rx3_div16p5_out,
    scan_rx3_dpll_clk,
    scan_rx3_dpll_in,
    scan_rx3_dpll_out,
    scan_rx3_dword_clk,
    scan_rx3_dword_in,
    scan_rx3_dword_out,
    scan_rx3_scope_clk,
    scan_rx3_scope_in,
    scan_rx3_scope_out,
    scan_rx3_stat_clk,
    scan_rx3_stat_in,
    scan_rx3_stat_out,
    scan_rx3_word_clk,
    scan_rx3_word_in,
    scan_rx3_word_out,
    scan_set_rst,
    scan_shift,
    scan_shift_cg,
    scan_tx0_ana_dword_clk,
    scan_tx0_ana_dword_in,
    scan_tx0_ana_dword_out,
    scan_tx0_ana_word_clk,
    scan_tx0_ana_word_in,
    scan_tx0_ana_word_out,
    scan_tx0_asic_dword_clk,
    scan_tx0_asic_dword_in,
    scan_tx0_asic_dword_out,
    scan_tx0_in,
    scan_tx0_out,
    scan_tx1_ana_dword_clk,
    scan_tx1_ana_dword_in,
    scan_tx1_ana_dword_out,
    scan_tx1_ana_word_clk,
    scan_tx1_ana_word_in,
    scan_tx1_ana_word_out,
    scan_tx1_asic_dword_clk,
    scan_tx1_asic_dword_in,
    scan_tx1_asic_dword_out,
    scan_tx1_in,
    scan_tx1_out,
    scan_tx2_ana_dword_clk,
    scan_tx2_ana_dword_in,
    scan_tx2_ana_dword_out,
    scan_tx2_ana_word_clk,
    scan_tx2_ana_word_in,
    scan_tx2_ana_word_out,
    scan_tx2_asic_dword_clk,
    scan_tx2_asic_dword_in,
    scan_tx2_asic_dword_out,
    scan_tx2_in,
    scan_tx2_out,
    scan_tx3_ana_dword_clk,
    scan_tx3_ana_dword_in,
    scan_tx3_ana_dword_out,
    scan_tx3_ana_word_clk,
    scan_tx3_ana_word_in,
    scan_tx3_ana_word_out,
    scan_tx3_asic_dword_clk,
    scan_tx3_asic_dword_in,
    scan_tx3_asic_dword_out,
    scan_tx3_in,
    scan_tx3_out,
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_addr,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_bypass,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_clk,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_ext_ld_done,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_init_done,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_rd_data,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_rd_en,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_wr_data,
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    sram_wr_en,
`endif
    test_burnin,
`ifdef DWC_E12MP_X4NS_PMA_FLYOVER
    test_flyover_en,
`endif
    test_powerdown,

    tx0_req,
    tx0_ack, 

    tx1_req,
    tx1_ack,

    tx2_req,
    tx2_ack,

    tx3_req,
    tx3_ack, 

    tx0_m,
    tx0_p,
    tx0_reset,
    
    tx1_m,
    tx1_p,
    tx1_reset,
    
    tx2_m,
    tx2_p,
    tx2_reset,
    
    tx3_m,
    tx3_p,
    tx3_reset,

    lane_40Geth_ena,
//---------------MAC--------------------
    ref_ff_clk_630plus, 
    ref_clk,
    ff_clk,
    reg_clk,
    clk_rdy,
    sd_tx2rx_par_lb_en,

    mac_reset,          
    reset_reg_clk,      
    mac_reset_ref_clk, 
    mac_reset_ff_rx_clk,
    mac_reset_ff_tx_clk,
    xlaui_reset_rx_clk, 
    xlaui_reset_tx_clk, 
    xlaui_reset_ref_clk,
    xaui_reset_rx_clk,  
    xaui_reset_tx_clk,  
    // rf_2p_cfg_register ,
    // ram_dp_cfg_register ,
// AXI Interface
// -------------

  // TX Application interface
  // ------------------------
    axi_ttvalid,                            //  tVALID -> valid transaction
    axi_ttlast,                             //  tVALID -> last transaction for a frame
    axi_ttkeep,                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    axi_ttdata,                      //  tDATA  -> frame data, left aligned
    axi_ttready,                            //  tREADY -> interface backpressure
    axi_ttuser,

  // RX Application interface
  // ------------------------
    axi_rtvalid,                            //  tVALID -> valid transaction
    axi_rtlast,                             //  tVALID -> last transaction for a frame
    axi_rtkeep,                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    axi_rtdata,                      //  tDATA  -> frame data, left aligned
    axi_rtuser,                    //  tUSER  -> sideband data. 
    axi_rtready,                            //  tREADY -> interface backpressure

//  ------------------- //
//  Register Interfaces //
//  ------------------- //
  
  //  10Geth PCS
  //  ----------
  
    xpcs_reg_wren,                    //  Write Enable  
    xpcs_reg_rden,                    //  Read Enable  
    xpcs_reg_addr,             //  Register Address
    xpcs_reg_din,              //  Write Data  
    xpcs_reg_dout,             //  Read Data  
    xpcs_reg_busy,                    //  Interface Busy  

  //  40Geth PCS
  //  ----------
  
    xlpcs_reg_wren,                   //  Write Enable  
    xlpcs_reg_rden,                   //  Read Enable  
    xlpcs_reg_addr,            //  Register Address
    xlpcs_reg_din ,             //  Write Data  
    xlpcs_reg_dout,            //  Read Data  
    xlpcs_reg_busy,                   //  Interface Busy 

  //  MAC
  //  -----
    mac_reg_wren,                     //  Write Enable    
    mac_reg_rden,                     //  Read Enable     
    mac_reg_addr,               //  Register Address
    mac_reg_din,               //  Write Data      
    mac_reg_dout,              //  Read Data       
    mac_reg_busy,                     //  Interface Busy  
    mac_reg_lowp_ena,                 //  Low Power Generation

// XAUI PCS Status
// ---------------
    x_align_done,                     //  Lane Alignment Done
    x_disp_err,                 //  Disparity Error Indication
    x_char_err,                 //  Character Error Indication
    x_sync,                     //  Channel Synchronization Indication
    x_cg_align,                 //  Code Group Alignment Indication
    x_pat,                      //  Comma Detected Indication

// XLAUI PCS Status
// ----------------
    xl_ber_timer_done,                //  Hi BER measure window
    xl_block_lock,              //  Block lock state reached
    xl_align_done,                    //  Alignment marker lock state reached
    xl_hi_ber,                        //  High Bit Error

  //  Configuration
  //  -------------
    pcs_40Geth_ena,                   //  Enable 40Geth operation

//  ------------------------- //
//  100Geth PCS Mode Settings //
//  ------------------------- //

  //  MAC
  //  -----
    mac_lpi_txhold,                   //  Transmit Hold Command
    mac_tx_loc_fault,                 //  Force RS TX to send LF sequences
    mac_tx_rem_fault,                 //  Force RS TX to send RF sequences
    mac_tx_li_fault,                  //  Transmit Link Interruption Command
    mac_loc_fault,                    //  RX receives LF sequences
    mac_rem_fault,                    //  RX receives RF sequences
    mac_li_fault,                     //  Receive Link Interruption

    mac_tx_ts_val,                    //  Frame transmitted
    mac_tx_ts_id,                     //  ID of frame
    mac_tx_ts,                        //  Timestamp
    mac_frc_in_tx,                    //  Timestamp Timer (nanoseconds)
    mac_frc_in_rx,                    //  Timestamp Timer (nanoseconds)
    mac_pfc_mode,                     //  PFC Mode Indication
    mac_pause_on,                     //  Transmit Paused/Class Congestion Indication
    mac_xoff_gen                      //  Transmit Flow Control Command
);

//`include "tb_memories.v"
// port declarations
//phy
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
    input  [4:0] rx0_cdr_ppm_max ;
    wire   [4:0] rx0_cdr_ppm_max ;
    input  [4:0] rx1_cdr_ppm_max ;
    wire   [4:0] rx1_cdr_ppm_max ;
    input  [4:0] rx2_cdr_ppm_max ;
    wire   [4:0] rx2_cdr_ppm_max ;
    input  [4:0] rx3_cdr_ppm_max ;
    wire   [4:0] rx3_cdr_ppm_max ;

    output [5:0] rx0_ppm_drift ;
    wire   [5:0] rx0_ppm_drift ;
    output   rx0_ppm_drift_vld ;
    wire     rx0_ppm_drift_vld ;

    output [5:0] rx1_ppm_drift ;
    wire   [5:0] rx1_ppm_drift ;
    output   rx1_ppm_drift_vld ;
    wire     rx1_ppm_drift_vld ;

    output [5:0] rx2_ppm_drift ;
    wire   [5:0] rx2_ppm_drift ;
    output   rx2_ppm_drift_vld ;
    wire     rx2_ppm_drift_vld ;

    output [5:0] rx3_ppm_drift ;
    wire   [5:0] rx3_ppm_drift ;
    output   rx3_ppm_drift_vld ;
    wire     rx3_ppm_drift_vld ;
`endif

`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  vp;
    wire  vp;
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    inout  vpdig;
`endif
`ifdef DWC_PMA_PADS_PWRSW
`else
    wire  vpdig;
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  vph;
    wire  vph;
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    inout  vptx0;
`endif
`ifdef DWC_PMA_PADS_PWRSW
`else
    wire  vptx0;
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    inout  vptx1;
`endif
`ifdef DWC_PMA_PADS_PWRSW
`else
    wire  vptx1;
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    inout  vptx2;
`endif
`ifdef DWC_PMA_PADS_PWRSW
`else
    wire  vptx2;
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    inout  vptx3;
`endif
`ifdef DWC_PMA_PADS_PWRSW
`else
    wire  vptx3;
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  vsscore_0;
    wire  vsscore_0;
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  vsscore_1;
    wire  vsscore_1;
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  vsscore_2;
    wire  vsscore_2;
`endif
`ifdef DWC_PMA_PADS_PWRSW
    input  ana_pwr_en;
    wire  ana_pwr_en;
`endif
`ifdef DWC_PMA_PADS_PWRSW
    output  ana_pwr_stable;
    wire  ana_pwr_stable;
`endif
    inout  atb_f_p;
    wire  atb_f_p;
    inout  atb_s_m;
    wire  atb_s_m;
    inout  atb_s_p;
    wire  atb_s_p;
    input  bs_acmode;
    wire  bs_acmode;
    input  bs_actest;
    wire  bs_actest;
    input  bs_cdr;
    wire  bs_cdr;
    input  bs_ce;
    wire  bs_ce;
    input bs_rx_bigswing;
    wire bs_rx_bigswing;
    input  bs_rx_init;
    wire  bs_rx_init;
    input [4:0] bs_rx_level;
    wire [4:0] bs_rx_level;
    input  bs_sdr;
    wire  bs_sdr;
    input  bs_tdi;
    wire  bs_tdi;
    output  bs_tdo;
    wire  bs_tdo;
    input bs_tx_lowswing;
    wire bs_tx_lowswing;
    input  bs_udr;
    wire  bs_udr;
    output  cr_para_ack;
    wire  cr_para_ack;
    input [15:0] cr_para_addr;
    wire [15:0] cr_para_addr;
    input  cr_para_clk;
    wire  cr_para_clk;
    output [15:0] cr_para_rd_data;
    wire [15:0] cr_para_rd_data;
    input  cr_para_rd_en;
    wire  cr_para_rd_en;
    input  cr_para_sel;
    wire  cr_para_sel;
    input [15:0] cr_para_wr_data;
    wire [15:0] cr_para_wr_data;
    input  cr_para_wr_en;
    wire  cr_para_wr_en;
    output [1:0] dtb_out;
    wire [1:0] dtb_out;
`ifdef DWC_E12MP_X4NS_PG_PINS
    inout  gd;
    wire  gd;
`endif
    input  jtag_tck;
    wire  jtag_tck;
    input  jtag_tdi;
    wire  jtag_tdi;
    output  jtag_tdo;
    wire  jtag_tdo;
    output  jtag_tdo_en;
    wire  jtag_tdo_en;
    input  jtag_tms;
    wire  jtag_tms;
    input  jtag_trst_n;
    wire  jtag_trst_n;

    //power gating signals
    input pcs_pwr_stable;
    wire pcs_pwr_stable;
    input pg_mode_en;
    wire pg_mode_en;
    input pg_reset;
    wire pg_reset;
    input pma_pwr_stable;
    wire pma_pwr_stable;
    output pcs_pwr_en;
    wire pcs_pwr_en;
    output pma_pwr_en;
    wire pma_pwr_en;

    inout  ref_pad_clk_m; 
    wire  ref_pad_clk_m;
    inout  ref_pad_clk_p;
    wire  ref_pad_clk_p;
    input ref_repeat_clk_en;
    wire ref_repeat_clk_en;
    output  ref_repeat_clk_m;
    wire  ref_repeat_clk_m;
    output  ref_repeat_clk_p;
    wire  ref_repeat_clk_p;
    output  phy_ref_dig_clk;
    wire  phy_ref_dig_clk;
    input  phy_reset;
    wire  phy_reset;
    input ref_clk_en;
    wire  ref_clk_en;
    input ref_use_pad;
    wire ref_use_pad;
    input  ref_alt_clk_m;
    wire  ref_alt_clk_m;
    input  ref_alt_clk_p;
    wire  ref_alt_clk_p;
    output  ref_clk_req;
    wire  ref_clk_req;
    inout  resref;
    wire  resref;

    input rtune_req;
    wire rtune_req;
    output rtune_ack;
    wire rtune_ack;
    input res_ack_in;
    wire  res_ack_in;   
    output res_ack_out;
    wire  res_ack_out;
    input res_req_in;
    wire  res_req_in;
    output res_req_out;
    wire  res_req_out;

    input lanex_rx2tx_par_lb_en;
    wire lanex_rx2tx_par_lb_en;
    input lanex_tx2rx_ser_lb_en;
    wire lanex_tx2rx_ser_lb_en;

    input rx0_req;
    wire  rx0_req;
    output rx0_ack;
    wire  rx0_ack; 

    input rx1_req;
    wire  rx1_req;
    output rx1_ack;
    wire  rx1_ack;

    input rx2_req;
    wire  rx2_req;
    output rx2_ack;
    wire  rx2_ack;

    input rx3_req;
    wire  rx3_req;
    output rx3_ack;
    wire  rx3_ack;   

    inout  rx0_m;
    wire  rx0_m;
    inout  rx0_p;
    wire  rx0_p;
    input  rx0_reset;
    wire  rx0_reset;

    inout  rx1_m;
    wire  rx1_m;
    inout  rx1_p;
    wire  rx1_p;
    input  rx1_reset;
    wire  rx1_reset;

    inout  rx2_m;
    wire  rx2_m;
    inout  rx2_p;
    wire  rx2_p;
    input  rx2_reset;
    wire  rx2_reset;

    inout  rx3_m;
    wire  rx3_m;
    inout  rx3_p;
    wire  rx3_p;
    input  rx3_reset;
    wire  rx3_reset;
    input  scan_cr_clk;
    wire  scan_cr_clk;
    input [`DWC_E12MP_X4NS_PHY_X4_SCAN_CR-1:0] scan_cr_in;
    wire [`DWC_E12MP_X4NS_PHY_X4_SCAN_CR-1:0] scan_cr_in;
    output [`DWC_E12MP_X4NS_PHY_X4_SCAN_CR-1:0] scan_cr_out;
    wire [`DWC_E12MP_X4NS_PHY_X4_SCAN_CR-1:0] scan_cr_out;
    input  scan_mode;
    wire  scan_mode;
    input  scan_mplla_div16p5_clk;
    wire  scan_mplla_div16p5_clk;
    input  scan_mplla_div16p5_in;
    wire  scan_mplla_div16p5_in;
    output  scan_mplla_div16p5_out;
    wire  scan_mplla_div16p5_out;
    input  scan_mplla_div33_clk;
    wire  scan_mplla_div33_clk;
    input  scan_mplla_div66_clk;
    wire  scan_mplla_div66_clk;
    input  scan_mplla_div_clk;
    wire  scan_mplla_div_clk;
    input  scan_mplla_div_in;
    wire  scan_mplla_div_in;
    output  scan_mplla_div_out;
    wire  scan_mplla_div_out;
    input  scan_mplla_dword_clk;
    wire  scan_mplla_dword_clk;
    input  scan_mplla_dword_in;
    wire  scan_mplla_dword_in;
    output  scan_mplla_dword_out;
    wire  scan_mplla_dword_out;
    input  scan_mplla_fb_clk;
    wire  scan_mplla_fb_clk;
    input  scan_mplla_fb_in;
    wire  scan_mplla_fb_in;
    output  scan_mplla_fb_out;
    wire  scan_mplla_fb_out;
    input  scan_mplla_oword_clk;
    wire  scan_mplla_oword_clk;
    input  scan_mplla_qword_clk;
    wire  scan_mplla_qword_clk;
    input  scan_mplla_qword_in;
    wire  scan_mplla_qword_in;
    output  scan_mplla_qword_out;
    wire  scan_mplla_qword_out;
    input  scan_mplla_ref_clk;
    wire  scan_mplla_ref_clk;
    input  scan_mplla_ref_in;
    wire  scan_mplla_ref_in;
    output  scan_mplla_ref_out;
    wire  scan_mplla_ref_out;
    input  scan_mplla_ssc_clk;
    wire  scan_mplla_ssc_clk;
    input [1:0] scan_mplla_ssc_in;
    wire [1:0] scan_mplla_ssc_in;
    output [1:0] scan_mplla_ssc_out;
    wire [1:0] scan_mplla_ssc_out;
    input  scan_mplla_word_clk;
    wire  scan_mplla_word_clk;
    input  scan_mplla_word_in;
    wire  scan_mplla_word_in;
    output  scan_mplla_word_out;
    wire  scan_mplla_word_out;
    input  scan_mpllb_div_clk;
    wire  scan_mpllb_div_clk;
    input  scan_mpllb_div_in;
    wire  scan_mpllb_div_in;
    output  scan_mpllb_div_out;
    wire  scan_mpllb_div_out;
    input  scan_mpllb_dword_clk;
    wire  scan_mpllb_dword_clk;
    input  scan_mpllb_dword_in;
    wire  scan_mpllb_dword_in;
    output  scan_mpllb_dword_out;
    wire  scan_mpllb_dword_out;
    input  scan_mpllb_fb_clk;
    wire  scan_mpllb_fb_clk;
    input  scan_mpllb_fb_in;
    wire  scan_mpllb_fb_in;
    output  scan_mpllb_fb_out;
    wire  scan_mpllb_fb_out;
    input  scan_mpllb_oword_clk;
    wire  scan_mpllb_oword_clk;
    input  scan_mpllb_qword_clk;
    wire  scan_mpllb_qword_clk;
    input  scan_mpllb_qword_in;
    wire  scan_mpllb_qword_in;
    output  scan_mpllb_qword_out;
    wire  scan_mpllb_qword_out;
    input  scan_mpllb_ref_clk;
    wire  scan_mpllb_ref_clk;
    input  scan_mpllb_ref_in;
    wire  scan_mpllb_ref_in;
    output  scan_mpllb_ref_out;
    wire  scan_mpllb_ref_out;
    input  scan_mpllb_ssc_clk;
    wire  scan_mpllb_ssc_clk;
    input [1:0] scan_mpllb_ssc_in;
    wire [1:0] scan_mpllb_ssc_in;
    output [1:0] scan_mpllb_ssc_out;
    wire [1:0] scan_mpllb_ssc_out;
    input  scan_mpllb_word_clk;
    wire  scan_mpllb_word_clk;
    input  scan_mpllb_word_in;
    wire  scan_mpllb_word_in;
    output  scan_mpllb_word_out;
    wire  scan_mpllb_word_out;
    input  scan_ref_clk;
    wire  scan_ref_clk;
    input  scan_ref_dig_clk;
    wire  scan_ref_dig_clk;
    input [9:0] scan_ref_dig_in;
    wire [9:0] scan_ref_dig_in;
    output [9:0] scan_ref_dig_out;
    wire [9:0] scan_ref_dig_out;
    input  scan_ref_in;
    wire  scan_ref_in;
    output  scan_ref_out;
    wire  scan_ref_out;
    input  scan_ref_range_clk;
    wire  scan_ref_range_clk;
    input [`DWC_E12MP_X4NS_PHY_X4_SCAN_REF_RANGE-1:0] scan_ref_range_in;
    wire [`DWC_E12MP_X4NS_PHY_X4_SCAN_REF_RANGE-1:0] scan_ref_range_in;
    output [`DWC_E12MP_X4NS_PHY_X4_SCAN_REF_RANGE-1:0] scan_ref_range_out;
    wire [`DWC_E12MP_X4NS_PHY_X4_SCAN_REF_RANGE-1:0] scan_ref_range_out;
    input  scan_rx0_adpt_clk;
    wire  scan_rx0_adpt_clk;
    input [4:0] scan_rx0_adpt_in;
    wire [4:0] scan_rx0_adpt_in;
    output [4:0] scan_rx0_adpt_out;
    wire [4:0] scan_rx0_adpt_out;
    input  scan_rx0_asic_clk;
    wire  scan_rx0_asic_clk;
    input  scan_rx0_asic_in;
    wire  scan_rx0_asic_in;
    output  scan_rx0_asic_out;
    wire  scan_rx0_asic_out;
    input  scan_rx0_div16p5_clk;
    wire  scan_rx0_div16p5_clk;
    input  scan_rx0_div16p5_in;
    wire  scan_rx0_div16p5_in;
    output  scan_rx0_div16p5_out;
    wire  scan_rx0_div16p5_out;
    input  scan_rx0_dpll_clk;
    wire  scan_rx0_dpll_clk;
    input  scan_rx0_dpll_in;
    wire  scan_rx0_dpll_in;
    output  scan_rx0_dpll_out;
    wire  scan_rx0_dpll_out;
    input  scan_rx0_dword_clk;
    wire  scan_rx0_dword_clk;
    input [8:0] scan_rx0_dword_in;
    wire [8:0] scan_rx0_dword_in;
    output [8:0] scan_rx0_dword_out;
    wire [8:0] scan_rx0_dword_out;
    input  scan_rx0_scope_clk;
    wire  scan_rx0_scope_clk;
    input  scan_rx0_scope_in;
    wire  scan_rx0_scope_in;
    output  scan_rx0_scope_out;
    wire  scan_rx0_scope_out;
    input  scan_rx0_stat_clk;
    wire  scan_rx0_stat_clk;
    input [6:0] scan_rx0_stat_in;
    wire [6:0] scan_rx0_stat_in;
    output [6:0] scan_rx0_stat_out;
    wire [6:0] scan_rx0_stat_out;
    input  scan_rx0_word_clk;
    wire  scan_rx0_word_clk;
    input  scan_rx0_word_in;
    wire  scan_rx0_word_in;
    output  scan_rx0_word_out;
    wire  scan_rx0_word_out;
    input  scan_rx1_adpt_clk;
    wire  scan_rx1_adpt_clk;
    input [4:0] scan_rx1_adpt_in;
    wire [4:0] scan_rx1_adpt_in;
    output [4:0] scan_rx1_adpt_out;
    wire [4:0] scan_rx1_adpt_out;
    input  scan_rx1_asic_clk;
    wire  scan_rx1_asic_clk;
    input  scan_rx1_asic_in;
    wire  scan_rx1_asic_in;
    output  scan_rx1_asic_out;
    wire  scan_rx1_asic_out;
    input  scan_rx1_div16p5_clk;
    wire  scan_rx1_div16p5_clk;
    input  scan_rx1_div16p5_in;
    wire  scan_rx1_div16p5_in;
    output  scan_rx1_div16p5_out;
    wire  scan_rx1_div16p5_out;
    input  scan_rx1_dpll_clk;
    wire  scan_rx1_dpll_clk;
    input  scan_rx1_dpll_in;
    wire  scan_rx1_dpll_in;
    output  scan_rx1_dpll_out;
    wire  scan_rx1_dpll_out;
    input  scan_rx1_dword_clk;
    wire  scan_rx1_dword_clk;
    input [8:0] scan_rx1_dword_in;
    wire [8:0] scan_rx1_dword_in;
    output [8:0] scan_rx1_dword_out;
    wire [8:0] scan_rx1_dword_out;
    input  scan_rx1_scope_clk;
    wire  scan_rx1_scope_clk;
    input  scan_rx1_scope_in;
    wire  scan_rx1_scope_in;
    output  scan_rx1_scope_out;
    wire  scan_rx1_scope_out;
    input  scan_rx1_stat_clk;
    wire  scan_rx1_stat_clk;
    input [6:0] scan_rx1_stat_in;
    wire [6:0] scan_rx1_stat_in;
    output [6:0] scan_rx1_stat_out;
    wire [6:0] scan_rx1_stat_out;
    input  scan_rx1_word_clk;
    wire  scan_rx1_word_clk;
    input  scan_rx1_word_in;
    wire  scan_rx1_word_in;
    output  scan_rx1_word_out;
    wire  scan_rx1_word_out;
    input  scan_rx2_adpt_clk;
    wire  scan_rx2_adpt_clk;
    input [4:0] scan_rx2_adpt_in;
    wire [4:0] scan_rx2_adpt_in;
    output [4:0] scan_rx2_adpt_out;
    wire [4:0] scan_rx2_adpt_out;
    input  scan_rx2_asic_clk;
    wire  scan_rx2_asic_clk;
    input  scan_rx2_asic_in;
    wire  scan_rx2_asic_in;
    output  scan_rx2_asic_out;
    wire  scan_rx2_asic_out;
    input  scan_rx2_div16p5_clk;
    wire  scan_rx2_div16p5_clk;
    input  scan_rx2_div16p5_in;
    wire  scan_rx2_div16p5_in;
    output  scan_rx2_div16p5_out;
    wire  scan_rx2_div16p5_out;
    input  scan_rx2_dpll_clk;
    wire  scan_rx2_dpll_clk;
    input  scan_rx2_dpll_in;
    wire  scan_rx2_dpll_in;
    output  scan_rx2_dpll_out;
    wire  scan_rx2_dpll_out;
    input  scan_rx2_dword_clk;
    wire  scan_rx2_dword_clk;
    input [8:0] scan_rx2_dword_in;
    wire [8:0] scan_rx2_dword_in;
    output [8:0] scan_rx2_dword_out;
    wire [8:0] scan_rx2_dword_out;
    input  scan_rx2_scope_clk;
    wire  scan_rx2_scope_clk;
    input  scan_rx2_scope_in;
    wire  scan_rx2_scope_in;
    output  scan_rx2_scope_out;
    wire  scan_rx2_scope_out;
    input  scan_rx2_stat_clk;
    wire  scan_rx2_stat_clk;
    input [6:0] scan_rx2_stat_in;
    wire [6:0] scan_rx2_stat_in;
    output [6:0] scan_rx2_stat_out;
    wire [6:0] scan_rx2_stat_out;
    input  scan_rx2_word_clk;
    wire  scan_rx2_word_clk;
    input  scan_rx2_word_in;
    wire  scan_rx2_word_in;
    output  scan_rx2_word_out;
    wire  scan_rx2_word_out;
    input  scan_rx3_adpt_clk;
    wire  scan_rx3_adpt_clk;
    input [4:0] scan_rx3_adpt_in;
    wire [4:0] scan_rx3_adpt_in;
    output [4:0] scan_rx3_adpt_out;
    wire [4:0] scan_rx3_adpt_out;
    input  scan_rx3_asic_clk;
    wire  scan_rx3_asic_clk;
    input  scan_rx3_asic_in;
    wire  scan_rx3_asic_in;
    output  scan_rx3_asic_out;
    wire  scan_rx3_asic_out;
    input  scan_rx3_div16p5_clk;
    wire  scan_rx3_div16p5_clk;
    input  scan_rx3_div16p5_in;
    wire  scan_rx3_div16p5_in;
    output  scan_rx3_div16p5_out;
    wire  scan_rx3_div16p5_out;
    input  scan_rx3_dpll_clk;
    wire  scan_rx3_dpll_clk;
    input  scan_rx3_dpll_in;
    wire  scan_rx3_dpll_in;
    output  scan_rx3_dpll_out;
    wire  scan_rx3_dpll_out;
    input  scan_rx3_dword_clk;
    wire  scan_rx3_dword_clk;
    input [8:0] scan_rx3_dword_in;
    wire [8:0] scan_rx3_dword_in;
    output [8:0] scan_rx3_dword_out;
    wire [8:0] scan_rx3_dword_out;
    input  scan_rx3_scope_clk;
    wire  scan_rx3_scope_clk;
    input  scan_rx3_scope_in;
    wire  scan_rx3_scope_in;
    output  scan_rx3_scope_out;
    wire  scan_rx3_scope_out;
    input  scan_rx3_stat_clk;
    wire  scan_rx3_stat_clk;
    input [6:0] scan_rx3_stat_in;
    wire [6:0] scan_rx3_stat_in;
    output [6:0] scan_rx3_stat_out;
    wire [6:0] scan_rx3_stat_out;
    input  scan_rx3_word_clk;
    wire  scan_rx3_word_clk;
    input  scan_rx3_word_in;
    wire  scan_rx3_word_in;
    output  scan_rx3_word_out;
    wire  scan_rx3_word_out;
    input  scan_set_rst;
    wire  scan_set_rst;
    input  scan_shift;
    wire  scan_shift;
    input  scan_shift_cg;
    wire  scan_shift_cg;
    input  scan_tx0_ana_dword_clk;
    wire  scan_tx0_ana_dword_clk;
    input  scan_tx0_ana_dword_in;
    wire  scan_tx0_ana_dword_in;
    output  scan_tx0_ana_dword_out;
    wire  scan_tx0_ana_dword_out;
    input  scan_tx0_ana_word_clk;
    wire  scan_tx0_ana_word_clk;
    input  scan_tx0_ana_word_in;
    wire  scan_tx0_ana_word_in;
    output  scan_tx0_ana_word_out;
    wire  scan_tx0_ana_word_out;
    input  scan_tx0_asic_dword_clk;
    wire  scan_tx0_asic_dword_clk;
    input  scan_tx0_asic_dword_in;
    wire  scan_tx0_asic_dword_in;
    output  scan_tx0_asic_dword_out;
    wire  scan_tx0_asic_dword_out;
    input [1:0] scan_tx0_in;
    wire [1:0] scan_tx0_in;
    output [1:0] scan_tx0_out;
    wire [1:0] scan_tx0_out;
    input  scan_tx1_ana_dword_clk;
    wire  scan_tx1_ana_dword_clk;
    input  scan_tx1_ana_dword_in;
    wire  scan_tx1_ana_dword_in;
    output  scan_tx1_ana_dword_out;
    wire  scan_tx1_ana_dword_out;
    input  scan_tx1_ana_word_clk;
    wire  scan_tx1_ana_word_clk;
    input  scan_tx1_ana_word_in;
    wire  scan_tx1_ana_word_in;
    output  scan_tx1_ana_word_out;
    wire  scan_tx1_ana_word_out;
    input  scan_tx1_asic_dword_clk;
    wire  scan_tx1_asic_dword_clk;
    input  scan_tx1_asic_dword_in;
    wire  scan_tx1_asic_dword_in;
    output  scan_tx1_asic_dword_out;
    wire  scan_tx1_asic_dword_out;
    input [1:0] scan_tx1_in;
    wire [1:0] scan_tx1_in;
    output [1:0] scan_tx1_out;
    wire [1:0] scan_tx1_out;
    input  scan_tx2_ana_dword_clk;
    wire  scan_tx2_ana_dword_clk;
    input  scan_tx2_ana_dword_in;
    wire  scan_tx2_ana_dword_in;
    output  scan_tx2_ana_dword_out;
    wire  scan_tx2_ana_dword_out;
    input  scan_tx2_ana_word_clk;
    wire  scan_tx2_ana_word_clk;
    input  scan_tx2_ana_word_in;
    wire  scan_tx2_ana_word_in;
    output  scan_tx2_ana_word_out;
    wire  scan_tx2_ana_word_out;
    input  scan_tx2_asic_dword_clk;
    wire  scan_tx2_asic_dword_clk;
    input  scan_tx2_asic_dword_in;
    wire  scan_tx2_asic_dword_in;
    output  scan_tx2_asic_dword_out;
    wire  scan_tx2_asic_dword_out;
    input [1:0] scan_tx2_in;
    wire [1:0] scan_tx2_in;
    output [1:0] scan_tx2_out;
    wire [1:0] scan_tx2_out;
    input  scan_tx3_ana_dword_clk;
    wire  scan_tx3_ana_dword_clk;
    input  scan_tx3_ana_dword_in;
    wire  scan_tx3_ana_dword_in;
    output  scan_tx3_ana_dword_out;
    wire  scan_tx3_ana_dword_out;
    input  scan_tx3_ana_word_clk;
    wire  scan_tx3_ana_word_clk;
    input  scan_tx3_ana_word_in;
    wire  scan_tx3_ana_word_in;
    output  scan_tx3_ana_word_out;
    wire  scan_tx3_ana_word_out;
    input  scan_tx3_asic_dword_clk;
    wire  scan_tx3_asic_dword_clk;
    input  scan_tx3_asic_dword_in;
    wire  scan_tx3_asic_dword_in;
    output  scan_tx3_asic_dword_out;
    wire  scan_tx3_asic_dword_out;
    input [1:0] scan_tx3_in;
    wire [1:0] scan_tx3_in;
    output [1:0] scan_tx3_out;
    wire [1:0] scan_tx3_out;
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output [11:0] sram_addr;
    wire [11:0] sram_addr;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    input  sram_bypass;
    wire  sram_bypass;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output  sram_clk;
    wire  sram_clk;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    input  sram_ext_ld_done;
    wire  sram_ext_ld_done;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output  sram_init_done;
    wire  sram_init_done;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    input [15:0] sram_rd_data;
    wire [15:0] sram_rd_data;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output  sram_rd_en;
    wire  sram_rd_en;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output [15:0] sram_wr_data;
    wire [15:0] sram_wr_data;
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    output  sram_wr_en;
    wire  sram_wr_en;
`endif
    input  test_burnin;
    wire  test_burnin;
`ifdef DWC_E12MP_X4NS_PMA_FLYOVER
    input  test_flyover_en;
    wire  test_flyover_en;
`endif
    input  test_powerdown;
    wire  test_powerdown;

    input tx0_req;
    wire  tx0_req;
    output tx0_ack;
    wire  tx0_ack; 

    input tx1_req;
    wire  tx1_req;
    output tx1_ack;
    wire  tx1_ack;

    input tx2_req;
    wire  tx2_req;
    output tx2_ack;
    wire  tx2_ack;

    input tx3_req;
    wire  tx3_req;
    output tx3_ack;
    wire  tx3_ack;  

    inout  tx0_m;
    wire  tx0_m;
    inout  tx0_p;
    wire  tx0_p;

    input  tx0_reset;
    wire  tx0_reset;

    inout  tx1_m;
    wire  tx1_m;
    inout  tx1_p;
    wire  tx1_p;

    input  tx1_reset;
    wire  tx1_reset;

    inout  tx2_m;
    wire  tx2_m;
    inout  tx2_p;
    wire  tx2_p;

    input  tx2_reset;
    wire  tx2_reset;
    
    inout tx3_m;
    wire  tx3_m;
    inout  tx3_p;
    wire  tx3_p;

    input  tx3_reset;
    wire  tx3_reset;

    input lane_40Geth_ena;
    wire lane_40Geth_ena;
//mac
// input  [6:0]     rf_2p_cfg_register;
// input  [11:0]    ram_dp_cfg_register;
// AXI Interface
// -------------

  // TX Application interface
  // ------------------------
    input   axi_ttvalid;                            //  tVALID -> valid transaction
    input   axi_ttlast;                             //  tVALID -> last transaction for a frame
    input   [7:0] axi_ttkeep;                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    input   [63:0] axi_ttdata;                      //  tDATA  -> frame data, left aligned
    output   axi_ttready;                            //  tREADY -> interface backpressure
    input   [6:0] axi_ttuser;
    wire    axi_ttvalid;                            //  tVALID -> valid transaction
    wire    axi_ttlast;                             //  tVALID -> last transaction for a frame
    wire    [7:0] axi_ttkeep;                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    wire    [63:0] axi_ttdata;                      //  tDATA  -> frame data, left aligned
    wire    axi_ttready;                            //  tREADY -> interface backpressure
    wire    [6:0] axi_ttuser;

  // RX Application interface
  // ------------------------

    output  axi_rtvalid;                            //  tVALID -> valid transaction
    output  axi_rtlast;                             //  tVALID -> last transaction for a frame
    output  [7:0] axi_rtkeep;                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    output  [63:0] axi_rtdata;                      //  tDATA  -> frame data, left aligned
    output  [90-1:0] axi_rtuser;                    //  tUSER  -> sideband data. 
    input  axi_rtready;                            //  tREADY -> interface backpressure
    wire    axi_rtvalid;                            //  tVALID -> valid transaction
    wire    axi_rtlast;                             //  tVALID -> last transaction for a frame
    wire    [7:0] axi_rtkeep;                       //  tKEEP  -> valid byte qualifier, 1 bit per byte in tdata
    wire    [63:0] axi_rtdata;                      //  tDATA  -> frame data, left aligned
    wire    [90-1:0] axi_rtuser;                    //  tUSER  -> sideband data. 
    wire    axi_rtready;                            //  tREADY -> interface backpressure

//  ------------------- //
//  Register Interfaces //
//  ------------------- //
    input  ref_ff_clk_630plus;
    output ref_clk;                                                //  Reference Clock
    output ff_clk;                                                 //  FIFO Clock
    input  reg_clk;                                                //  Register Interface Clock
    output clk_rdy;
    input  sd_tx2rx_par_lb_en;
    wire   ref_ff_clk_630plus; 
    wire   ref_clk;                                                //  Reference Clock
    wire   ff_clk;                                                 //  FIFO Clock
    wire   reg_clk;                                                //  Register Interface Clock
    wire   clk_rdy;
    wire   sd_tx2rx_par_lb_en;
//reset
    input         mac_reset            ;
    input         reset_reg_clk        ;    
    input         mac_reset_ref_clk    ;    
    input         mac_reset_ff_rx_clk  ;    
    input         mac_reset_ff_tx_clk  ;    
    input [3:0]   xlaui_reset_rx_clk   ;
    input         xlaui_reset_tx_clk   ;    
    input         xlaui_reset_ref_clk  ;    
    input [3:0]   xaui_reset_rx_clk    ;
    input         xaui_reset_tx_clk    ; 

    wire          mac_reset            ;    
    wire          reset_reg_clk        ;    
    wire          mac_reset_ref_clk    ;    
    wire          mac_reset_ff_rx_clk  ;    
    wire          mac_reset_ff_tx_clk  ;    
    wire  [3:0]   xlaui_reset_rx_clk   ;
    wire          xlaui_reset_tx_clk   ;    
    wire          xlaui_reset_ref_clk  ;    
    wire  [3:0]   xaui_reset_rx_clk    ;
    wire          xaui_reset_tx_clk    ; 
  //  10Geth PCS
  //  ----------

    input xpcs_reg_wren;                    //  Write Enable  
    input xpcs_reg_rden;                    //  Read Enable  
    input [15:0] xpcs_reg_addr;             //  Register Address
    input [15:0] xpcs_reg_din;              //  Write Data  
    output [15:0] xpcs_reg_dout;             //  Read Data  
    output xpcs_reg_busy;                    //  Interface Busy   
    wire xpcs_reg_wren;                    //  Write Enable  
    wire xpcs_reg_rden;                    //  Read Enable  
    wire [15:0] xpcs_reg_addr;             //  Register Address
    wire [15:0] xpcs_reg_din;              //  Write Data  
    wire [15:0] xpcs_reg_dout;             //  Read Data  
    wire xpcs_reg_busy;                    //  Interface Busy  

  //  40Geth PCS
  //  ----------
    input xlpcs_reg_wren;                   //  Write Enable  
    input xlpcs_reg_rden;                   //  Read Enable  
    input [15:0] xlpcs_reg_addr;            //  Register Address
    input [15:0] xlpcs_reg_din;             //  Write Data  
    output [15:0] xlpcs_reg_dout;            //  Read Data  
    output xlpcs_reg_busy;                   //  Interface Busy   
    wire xlpcs_reg_wren;                   //  Write Enable  
    wire xlpcs_reg_rden;                   //  Read Enable  
    wire [15:0] xlpcs_reg_addr;            //  Register Address
    wire [15:0] xlpcs_reg_din;             //  Write Data  
    wire [15:0] xlpcs_reg_dout;            //  Read Data  
    wire xlpcs_reg_busy;                   //  Interface Busy 

  //  MAC
  //  -----
    input mac_reg_wren;                     //  Write Enable    
    input mac_reg_rden;                     //  Read Enable     
    input [7:0] mac_reg_addr;               //  Register Address
    input [31:0] mac_reg_din;               //  Write Data      
    output [31:0] mac_reg_dout;              //  Read Data       
    output mac_reg_busy;                     //  Interface Busy  
    input mac_reg_lowp_ena;                 //  Low Power Generation
    wire mac_reg_wren;                     //  Write Enable    
    wire mac_reg_rden;                     //  Read Enable     
    wire [7:0] mac_reg_addr;               //  Register Address
    wire [31:0] mac_reg_din;               //  Write Data      
    wire [31:0] mac_reg_dout;              //  Read Data       
    wire mac_reg_busy;                     //  Interface Busy  
    wire mac_reg_lowp_ena;                 //  Low Power Generation

// XAUI PCS Status
// ---------------

    output x_align_done;                     //  Lane Alignment Done
    output [3:0] x_disp_err;                 //  Disparity Error Indication
    output [3:0] x_char_err;                 //  Character Error Indication
    output [3:0] x_sync;                     //  Channel Synchronization Indication
    output [3:0] x_cg_align;                 //  Code Group Alignment Indication
    output [3:0] x_pat;                      //  Comma Detected Indication
    wire x_align_done;                     //  Lane Alignment Done
    wire [3:0] x_disp_err;                 //  Disparity Error Indication
    wire [3:0] x_char_err;                 //  Character Error Indication
    wire [3:0] x_sync;                     //  Channel Synchronization Indication
    wire [3:0] x_cg_align;                 //  Code Group Alignment Indication
    wire [3:0] x_pat;                      //  Comma Detected Indication

// XLAUI PCS Status
// ----------------
    output xl_ber_timer_done;                //  Hi BER measure window
    output [3:0] xl_block_lock;              //  Block lock state reached
    output xl_align_done;                    //  Alignment marker lock state reached
    output xl_hi_ber;                        //  High Bit Error
    wire xl_ber_timer_done;                //  Hi BER measure window
    wire [3:0] xl_block_lock;              //  Block lock state reached
    wire xl_align_done;                    //  Alignment marker lock state reached
    wire xl_hi_ber;                        //  High Bit Error

//  Configuration
//  -------------

    input pcs_40Geth_ena;
    wire pcs_40Geth_ena;                   //  Enable 40Geth operation

//  ------------------------- //
//  100Geth PCS Mode Settings //
//  ------------------------- //

  //  MAC
  //  -----
    input mac_lpi_txhold;
    wire mac_lpi_txhold;                   //  Transmit Hold Command
    input mac_tx_loc_fault;
    wire mac_tx_loc_fault;                 //  Force RS TX to send LF sequences
    input mac_tx_rem_fault;
    wire mac_tx_rem_fault;                 //  Force RS TX to send RF sequences
    input mac_tx_li_fault;
    wire mac_tx_li_fault;                  //  Transmit Link Interruption Command
    output mac_loc_fault;
    wire mac_loc_fault;                    //  RX receives LF sequences
    output mac_rem_fault;
    wire mac_rem_fault;                    //  RX receives RF sequences
    output mac_li_fault;
    wire mac_li_fault;                     //  Receive Link Interruption


    output mac_tx_ts_val;
    wire mac_tx_ts_val;                    //  Frame transmitted
    output [4-1:0] mac_tx_ts_id;
    wire [4-1:0] mac_tx_ts_id;             //  ID of frame
    output [64-1:0] mac_tx_ts;
    wire [64-1:0] mac_tx_ts;               //  Timestamp
    input [63:0] mac_frc_in_tx;
    wire [63:0] mac_frc_in_tx;             //  Timestamp Timer (nanoseconds)
    input [63:0] mac_frc_in_rx;
    wire [63:0] mac_frc_in_rx;             //  Timestamp Timer (nanoseconds)
    output mac_pfc_mode;
    wire mac_pfc_mode;                     //  PFC Mode Indication
    output [7:0] mac_pause_on;
    wire [7:0] mac_pause_on;               //  Transmit Paused/Class Congestion Indication
    input [7:0] mac_xoff_gen;
    wire [7:0] mac_xoff_gen;               //  Transmit Flow Control Command

//*******************
//DEFINE PARAMETER
//*******************
//Parameter(s) 

//*********************
//INNER SIGNAL DECLARATION
//*********************
//REGS

// reg [19:0] rx0_data_dl;
// reg [19:0] rx1_data_dl;
// reg [19:0] rx2_data_dl;
// reg [19:0] rx3_data_dl;

//WIRES
 
//phy congfiger------assigned in phy_config.v
wire            bs_rx_bigswing_in      ;
wire            bs_tx_lowswing_in      ;

wire [10:0]     mplla_bandwidth        ;
wire            mplla_div10_clk_en     ;
wire            mplla_div16p5_clk_en   ;
wire            mplla_div8_clk_en      ;
wire            mplla_div_clk_en       ;
wire [ 6:0]     mplla_div_multiplier   ;
wire            mplla_force_en         ;
wire [ 8:0]     mplla_fracn_ctrl       ;
wire            mplla_init_cal_disable ;
wire [ 7:0]     mplla_multiplier       ;
wire [ 2:0]     mplla_ssc_clk_sel      ;
wire            mplla_ssc_en           ;
wire [ 2:0]     mplla_ssc_range        ;
wire [10:0]     mpllb_bandwidth        ;
wire            mpllb_div10_clk_en     ;
wire            mpllb_div8_clk_en      ;
wire            mpllb_div_clk_en       ;
wire [ 6:0]     mpllb_div_multiplier   ;
wire            mpllb_force_en         ;
wire [ 8:0]     mpllb_fracn_ctrl       ;
wire            mpllb_init_cal_disable ;
wire [ 7:0]     mpllb_multiplier       ;
wire [ 2:0]     mpllb_ssc_clk_sel      ;
wire            mpllb_ssc_en           ;
wire [ 2:0]     mpllb_ssc_range        ;


wire            ref_clk_div2_en        ;
wire            ref_clk_mplla_div2_en  ; 
wire            ref_clk_mpllb_div2_en  ;
wire [ 2:0]     ref_range              ;


wire            rxx_adapt_afe_en       ;
wire            rxx_adapt_cont         ;
wire            rxx_adapt_dfe_en       ;
wire            rxx_adapt_req          ;
wire            rxx_align_en           ;
wire            rxx_cdr_ssc_en         ;
wire            rxx_cdr_track_en       ;
wire            rxx_cdr_vco_lowfreq    ;
wire            rxx_clk_shift          ;
wire            rxx_data_en            ;
wire            rxx_disable            ;
wire            rxx_div16p5_clk_en     ;
wire [ 2:0]     rxx_eq_att_lvl         ;
wire [ 4:0]     rxx_eq_ctle_boost      ;
wire [ 2:0]     rxx_eq_ctle_pole       ;
wire [ 7:0]     rxx_eq_dfe_tap1        ;
wire [ 3:0]     rxx_eq_vga1_gain       ;
wire [ 3:0]     rxx_eq_vga2_gain       ;
wire            rxx_invert             ;
wire            rxx_los_lfps_en        ;
wire [ 2:0]     rxx_los_threshold      ;
wire            rxx_lpd                ;
wire            rxx_offcan_cont        ;
wire [ 1:0]     rxx_pstate             ;
wire [ 1:0]     rxx_rate               ;
wire [ 5:0]     rxx_ref_ld_val         ;
wire            rxx_term_acdc          ;
wire            rxx_term_en            ;
wire [12:0]     rxx_vco_ld_val         ;
wire [ 1:0]     rxx_width              ;

wire            txx_beacon_en          ;
wire            txx_data_en            ;
wire            txx_detrx_req          ;
wire            txx_disable            ;
wire [ 5:0]     txx_eq_main            ;
wire [ 5:0]     txx_eq_post            ;
wire [ 5:0]     txx_eq_pre             ;
wire [ 3:0]     txx_iboost_lvl         ;
wire            txx_invert             ;
wire            txx_lpd                ;
wire            txx_mpll_en            ;
wire            txx_mpllb_sel          ;
wire [ 1:0]     txx_pstate             ;
wire [ 2:0]     txx_rate               ;
wire            txx_vboost_en          ;
wire [ 1:0]     txx_width              ;

wire [ 2:0]     tx_vboost_lvl          ;
wire [ 4:0]     rx_vref_ctrl           ;
//*******************************

wire  mplla_div16p5_clk;
wire  mplla_div33_clk;
wire  mplla_div66_clk;
wire  mplla_div_clk;
wire  mplla_dword_clk;
wire  mplla_oword_clk;
wire  mplla_qword_clk;
wire  mplla_state;
wire  mplla_word_clk;

wire  mpllb_div_clk;
wire  mpllb_dword_clk;
wire  mpllb_oword_clk;
wire  mpllb_qword_clk;
wire  mpllb_state;
wire  mpllb_word_clk;
    

wire  ref_dig_fr_clk;

wire  rx0_adapt_ack;
wire [7:0] rx0_adapt_fom;

wire  rx0_clk;
wire [19:0] rx0_data;
wire  rx0_div16p5_clk;
wire  rx0_los;

wire [1:0] rx0_txmain_dir;
wire [1:0] rx0_txpost_dir;
wire [1:0] rx0_txpre_dir;
wire  rx0_valid;

wire  rx1_adapt_ack;
wire [7:0] rx1_adapt_fom;

wire  rx1_clk;
wire [19:0] rx1_data;
wire  rx1_div16p5_clk;
wire  rx1_los;

wire [1:0] rx1_txmain_dir;
wire [1:0] rx1_txpost_dir;
wire [1:0] rx1_txpre_dir;
wire  rx1_valid;

wire  rx2_adapt_ack;
wire [7:0] rx2_adapt_fom;

wire  rx2_clk;
wire [19:0] rx2_data;
wire  rx2_div16p5_clk;
wire  rx2_los;

wire [1:0] rx2_txmain_dir;
wire [1:0] rx2_txpost_dir;
wire [1:0] rx2_txpre_dir;
wire  rx2_valid;

wire  rx3_adapt_ack;
wire [7:0] rx3_adapt_fom;

wire  rx3_clk;
wire [19:0] rx3_data;
wire  rx3_div16p5_clk;
wire  rx3_los;


wire [1:0] rx3_txmain_dir;
wire [1:0] rx3_txpost_dir;
wire [1:0] rx3_txpre_dir;
wire  rx3_valid;


wire  tx0_clk;
wire  tx0_clk_rdy;
wire [19:0] tx0_data;
wire  tx0_detrx_result;


wire  tx0_master_mplla_state;
wire  tx0_master_mpllb_state;

wire  tx0_word_clk;

wire  tx1_clk;
wire  tx1_clk_rdy;
wire [19:0] tx1_data;
wire  tx1_detrx_result;

wire  tx1_master_mplla_state;
wire  tx1_master_mpllb_state;
   
wire  tx1_word_clk;

wire  tx2_clk;
wire  tx2_clk_rdy;
wire [19:0] tx2_data;
wire  tx2_detrx_result;

wire  tx2_master_mplla_state;
wire  tx2_master_mpllb_state;

wire  tx2_word_clk;

wire  tx3_clk;
wire  tx3_clk_rdy;
wire [19:0] tx3_data;
wire  tx3_detrx_result;

wire  tx3_master_mplla_state;
wire  tx3_master_mpllb_state;

wire  tx3_word_clk;
// MAC&PCS signals
//reset

wire          reset_reg_clk_in        ;    
wire          mac_reset_ref_clk_in    ;    
wire          mac_reset_ff_rx_clk_in  ;    
wire          mac_reset_ff_tx_clk_in  ;    
wire  [3:0]   xlaui_reset_rx_clk_in   ;
wire          xlaui_reset_tx_clk_in   ;    
wire          xlaui_reset_ref_clk_in  ;    
wire  [3:0]   xaui_reset_rx_clk_in    ;
wire          xaui_reset_tx_clk_in    ;    

wire          reset_reg_clk_temp        ;    
wire          mac_reset_ref_clk_temp    ;    
wire          mac_reset_ff_rx_clk_temp  ;    
wire          mac_reset_ff_tx_clk_temp  ;    
wire  [3:0]   xlaui_reset_rx_clk_temp   ;
wire          xlaui_reset_tx_clk_temp   ;    
wire          xlaui_reset_ref_clk_temp  ;    
wire  [3:0]   xaui_reset_rx_clk_temp    ;
wire          xaui_reset_tx_clk_temp    ; 
//serdes_interface
wire sd_tx_clk;                        //  PMA Transmit Clocks

wire sd0_rx_clk;                        //  PMA Receive Clocks
wire [19:0] sd0_tx;                     //  10/25/40/50Geth PCS PMA Transmit Lane Data
wire [19:0] sd0_rx;                     //  10/25/40/50Geth PCS PMA Receive Lane Data
wire signal_det0;                       //  Signal detect signal per Serdes lane

wire sd1_rx_clk;                        //  PMA Receive Clocks
wire [19:0] sd1_tx;                     //  10/25/40/50Geth PCS PMA Transmit Lane Data
wire [19:0] sd1_rx;                     //  10/25/40/50Geth PCS PMA Receive Lane Data
wire signal_det1;                       //  Signal detect signal per Serdes lane

wire sd2_rx_clk;                        //  PMA Receive Clocks
wire [19:0] sd2_tx;                     //  10/25/40/50Geth PCS PMA Transmit Lane Data
wire [19:0] sd2_rx;                     //  10/25/40/50Geth PCS PMA Receive Lane Data
wire signal_det2;                       //  Signal detect signal per Serdes lane

wire sd3_rx_clk;                        //  PMA Receive Clocks
wire [19:0] sd3_tx;                     //  10/25/40/50Geth PCS PMA Transmit Lane Data
wire [19:0] sd3_rx;                     //  10/25/40/50Geth PCS PMA Receive Lane Data
wire signal_det3;                       //  Signal detect signal per Serdes lane
// External Memory Interfaces //

// MAC Statistics
// --------------
wire    [6-1:0] rstm_raddr;                     //  Stats RX mem Read address (rxclk)
wire    rstm_rden;                              //  Stats RX mem read enable (rxclk)
wire    [64:0] rstm_rdata;                      //  Stats RX mem Read data (rxclk)
wire    rstm_wren;                              //  Stats RX mem write (rxclk)
wire    [6-1:0] rstm_waddr;                     //  Stats RX mem write address (rxclk)
wire    [64:0] rstm_wdata;                      //  Stats RX mem write data (rxclk)

wire    [6-1:0] tstm_raddr;                     //  Stats TX mem Read address (txclk)
wire    tstm_rden;                              //  Stats TX mem read enable (txclk)
wire    [64:0] tstm_rdata;                      //  Stats TX mem Read data (txclk)
wire    tstm_wren;                              //  Stats TX mem write (txclk)
wire    [6-1:0] tstm_waddr;                     //  Stats TX mem write address (txclk)
wire    [64:0] tstm_wdata;                      //  Stats TX mem write data (txclk)

// MAC FIFOs
// --------- 
wire    [5-1:0] rxd_raddr;                      //  RX Data FIFO read address (ff_rx_clk)
wire    rxd_rden;                               //  RX Data FIFO read enable (ff_rx_clk)
wire    [64-1:0] rxd_rdata;                     //  RX Data FIFO read data (ff_rx_clk)
wire    rxd_recc;                               //  RX Data FIFO read data ecc error (ff_rx_clk)
wire    rxd_wren;                               //  RX Data FIFO write (rx_clk)
wire    [5-1:0] rxd_waddr;                      //  RX Data FIFO write address (rx_clk)
wire    [64-1:0] rxd_wdata;                     //  RX Data FIFO write data (rx_clk)  

wire    [5-1:0] rxs_raddr;                      //  RX Status read address (ff_rx_clk)
wire    rxs_rden;                               //  RX Status read enable (ff_rx_clk)
wire    [42-1:0] rxs_rdata;                     //  RX Status read data (ff_rx_clk)
wire    rxs_wren;                               //  RX Status write (rx_clk)
wire    [5-1:0] rxs_waddr;                      //  RX Status write address (rx_clk)
wire    [42-1:0] rxs_wdata;                     //  RX Status write data (rx_clk)

wire    [5-1:0] rxp_raddr;                      //  RX Ts/Prb read address (ff_rx_clk)
wire    rxp_rden;                               //  RX Ts/Prb read enable (ff_rx_clk)
wire    [64-1:0] rxp_rdata;                     //  RX Ts/Prb read data (ff_rx_clk)
wire    rxp_wren;                               //  RX Ts/Prb write (rx_clk)
wire    [5-1:0] rxp_waddr;                      //  RX Ts/Prb write address (rx_clk)
wire    [64-1:0] rxp_wdata;                     //  RX Ts/Prb write data (rx_clk)

wire    [5-1:0] txd_raddr;                      //  TX Read address (tx_clk)
wire    txd_rden;                               //  TX read enable (tx_clk)
wire    [66-1:0] txd_rdata;                     //  TX Read data (tx_clk)
wire    txd_recc;                               //  TX Read data ecc error (tx_clk)
wire    txd_wren;                               //  TX write (ff_tx_clk)
wire    [5-1:0] txd_waddr;                      //  TX write addres (ff_tx_clk)
wire    [66-1:0] txd_wdata;                     //  TX write data (ff_tx_clk)

wire    [5-1:0] txs_raddr;                      //  TX Status Read address (tx_clk)
wire    txs_rden;                               //  TX Status read enable (tx_clk)
wire    [23-1:0] txs_rdata;                     //  TX Status Read data (tx_clk)
wire    txs_wren;                               //  TX Status write (ff_tx_clk)
wire    [5-1:0] txs_waddr;                      //  TX Status write addres (ff_tx_clk)
wire    [23-1:0] txs_wdata;                     //  TX Status write data (ff_tx_clk)

//*********************
//INSTANTCE MODULE
//*********************

dwc_e12mp_phy_x4_ns U_phy(
`ifdef DWC_E12MP_X4NS_RX_CDR_PPM_DETECTOR_ADDED
    .rx0_cdr_ppm_max   ( rx0_cdr_ppm_max   ),
    .rx0_ppm_drift     ( rx0_ppm_drift     ),
    .rx0_ppm_drift_vld ( rx0_ppm_drift_vld ),
    .rx1_cdr_ppm_max   ( rx1_cdr_ppm_max   ),
    .rx1_ppm_drift     ( rx1_ppm_drift     ),
    .rx1_ppm_drift_vld ( rx1_ppm_drift_vld ),
    .rx2_cdr_ppm_max   ( rx2_cdr_ppm_max   ),
    .rx2_ppm_drift     ( rx2_ppm_drift     ),
    .rx2_ppm_drift_vld ( rx2_ppm_drift_vld ),
    .rx3_cdr_ppm_max   ( rx3_cdr_ppm_max   ),
    .rx3_ppm_drift     ( rx3_ppm_drift     ),
    .rx3_ppm_drift_vld ( rx3_ppm_drift_vld ),
`endif

`ifdef DWC_E12MP_X4NS_PG_PINS
    .vp(vp),
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    .vpdig(vpdig),
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    .vph(vph),
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    .vptx0(vptx0),
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    .vptx1(vptx1),
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    .vptx2(vptx2),
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
`ifdef DWC_PMA_PADS_PWRSW
`else
    .vptx3(vptx3),
`endif
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    .vsscore_0(vsscore_0),
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    .vsscore_1(vsscore_1),
`endif
`ifdef DWC_E12MP_X4NS_PG_PINS
    .vsscore_2(vsscore_2),
`endif
    .atb_f_p(atb_f_p),
    .atb_s_m(atb_s_m),
    .atb_s_p(atb_s_p),
    .bs_acmode(bs_acmode),
    .bs_actest(bs_actest),
    .bs_cdr(bs_cdr),
    .bs_ce(bs_ce),
    .bs_rx_bigswing(bs_rx_bigswing_in),
    .bs_rx_init(bs_rx_init),
    .bs_rx_level(bs_rx_level),
    .bs_sdr(bs_sdr),
    .bs_tdi(bs_tdi),
    .bs_tdo(bs_tdo),
    .bs_tx_lowswing(bs_tx_lowswing_in),
    .bs_udr(bs_udr),
    .cr_para_ack(cr_para_ack),
    .cr_para_addr(cr_para_addr),
    .cr_para_clk(cr_para_clk),
    .cr_para_rd_data(cr_para_rd_data),
    .cr_para_rd_en(cr_para_rd_en),
    .cr_para_sel(cr_para_sel),
    .cr_para_wr_data(cr_para_wr_data),
    .cr_para_wr_en(cr_para_wr_en),
    .dtb_out(dtb_out),
`ifdef DWC_E12MP_X4NS_PG_PINS
    .gd(gd),
`endif
    .jtag_tck(jtag_tck),
    .jtag_tdi(jtag_tdi),
    .jtag_tdo(jtag_tdo),
    .jtag_tdo_en(jtag_tdo_en),
    .jtag_tms(jtag_tms),
    .jtag_trst_n(jtag_trst_n),
    .lane0_rx2tx_par_lb_en(lanex_rx2tx_par_lb_en),
    .lane0_tx2rx_ser_lb_en(lanex_tx2rx_ser_lb_en),
    .lane1_rx2tx_par_lb_en(lanex_rx2tx_par_lb_en),
    .lane1_tx2rx_ser_lb_en(lanex_tx2rx_ser_lb_en),
    .lane2_rx2tx_par_lb_en(lanex_rx2tx_par_lb_en),
    .lane2_tx2rx_ser_lb_en(lanex_tx2rx_ser_lb_en),
    .lane3_rx2tx_par_lb_en(lanex_rx2tx_par_lb_en),
    .lane3_tx2rx_ser_lb_en(lanex_tx2rx_ser_lb_en),
    .mplla_bandwidth(mplla_bandwidth),
    .mplla_div10_clk_en(mplla_div10_clk_en),
    .mplla_div16p5_clk(mplla_div16p5_clk),
    .mplla_div16p5_clk_en(mplla_div16p5_clk_en),
    .mplla_div33_clk(mplla_div33_clk),
    .mplla_div66_clk(mplla_div66_clk),
    .mplla_div8_clk_en(mplla_div8_clk_en),
    .mplla_div_clk(mplla_div_clk),
    .mplla_div_clk_en(mplla_div_clk_en),
    .mplla_div_multiplier(mplla_div_multiplier),
    .mplla_dword_clk(mplla_dword_clk),
    .mplla_force_en(mplla_force_en),
    .mplla_fracn_ctrl(mplla_fracn_ctrl),
    .mplla_init_cal_disable(mplla_init_cal_disable),
    .mplla_multiplier(mplla_multiplier),
    .mplla_oword_clk(mplla_oword_clk),
    .mplla_qword_clk(mplla_qword_clk),
    .mplla_ssc_clk_sel(mplla_ssc_clk_sel),
    .mplla_ssc_en(mplla_ssc_en),
    .mplla_ssc_range(mplla_ssc_range),
    .mplla_state(mplla_state),
    .mplla_word_clk(mplla_word_clk),
    .mpllb_bandwidth(mpllb_bandwidth),
    .mpllb_div10_clk_en(mpllb_div10_clk_en),
    .mpllb_div8_clk_en(mpllb_div8_clk_en),
    .mpllb_div_clk(mpllb_div_clk),
    .mpllb_div_clk_en(mpllb_div_clk_en),
    .mpllb_div_multiplier(mpllb_div_multiplier),
    .mpllb_dword_clk(mpllb_dword_clk),
    .mpllb_force_en(mpllb_force_en),
    .mpllb_fracn_ctrl(mpllb_fracn_ctrl),
    .mpllb_init_cal_disable(mpllb_init_cal_disable),
    .mpllb_multiplier(mpllb_multiplier),
    .mpllb_oword_clk(mpllb_oword_clk),
    .mpllb_qword_clk(mpllb_qword_clk),
    .mpllb_ssc_clk_sel(mpllb_ssc_clk_sel),
    .mpllb_ssc_en(mpllb_ssc_en),
    .mpllb_ssc_range(mpllb_ssc_range),
    .mpllb_state(mpllb_state),
    .mpllb_word_clk(mpllb_word_clk),
    .pcs_pwr_en(pcs_pwr_en),//left floating
    .pcs_pwr_stable(pcs_pwr_stable),
    .pg_mode_en(pg_mode_en),
    .pg_reset(pg_reset),
    .phy_ref_dig_clk(phy_ref_dig_clk),
    .phy_reset(phy_reset),
    .pma_pwr_en(pma_pwr_en),//left floating,
    .pma_pwr_stable(pma_pwr_stable),
    .ref_alt_clk_m(ref_alt_clk_m),
    .ref_alt_clk_p(ref_alt_clk_p),
    .ref_clk_div2_en(ref_clk_div2_en),
    .ref_clk_en(ref_clk_en),
    .ref_clk_mplla_div2_en(ref_clk_mplla_div2_en),
    .ref_clk_mpllb_div2_en(ref_clk_mpllb_div2_en),
    .ref_clk_req(ref_clk_req),
    .ref_dig_fr_clk(ref_dig_fr_clk),
    .ref_pad_clk_m(ref_pad_clk_m),
    .ref_pad_clk_p(ref_pad_clk_p),
    .ref_range(ref_range),
    .ref_repeat_clk_en(ref_repeat_clk_en),
    .ref_repeat_clk_m(ref_repeat_clk_m),
    .ref_repeat_clk_p(ref_repeat_clk_p),
    .ref_use_pad(ref_use_pad),
    .res_ack_in(res_ack_in),
    .res_ack_out(res_ack_out),
    .res_req_in(res_req_in),
    .res_req_out(res_req_out),
    .resref(resref),
    .rtune_ack(rtune_ack),
    .rtune_req(rtune_req),
    .rx0_ack(rx0_ack),
    .rx0_adapt_ack(rx0_adapt_ack),
    .rx0_adapt_afe_en(rxx_adapt_afe_en),
    .rx0_adapt_cont(rxx_adapt_cont),
    .rx0_adapt_dfe_en(rxx_adapt_dfe_en),
    .rx0_adapt_fom(rx0_adapt_fom),
    .rx0_adapt_req(rxx_adapt_req),
    .rx0_align_en(rxx_align_en),
    .rx0_cdr_ssc_en(rxx_cdr_ssc_en),
    .rx0_cdr_track_en(rxx_cdr_track_en),
    .rx0_cdr_vco_lowfreq(rxx_cdr_vco_lowfreq),
    .rx0_clk(rx0_clk),
    .rx0_clk_shift(rxx_clk_shift),
    .rx0_data(rx0_data),
    .rx0_data_en(rxx_data_en),
    .rx0_disable(rxx_disable),
    .rx0_div16p5_clk(rx0_div16p5_clk),
    .rx0_div16p5_clk_en(rxx_div16p5_clk_en),
    .rx0_eq_att_lvl(rxx_eq_att_lvl),
    .rx0_eq_ctle_boost(rxx_eq_ctle_boost),
    .rx0_eq_ctle_pole(rxx_eq_ctle_pole),
    .rx0_eq_dfe_tap1(rxx_eq_dfe_tap1),
    .rx0_eq_vga1_gain(rxx_eq_vga1_gain),
    .rx0_eq_vga2_gain(rxx_eq_vga2_gain),
    .rx0_invert(rxx_invert),
    .rx0_los(rx0_los),
    .rx0_los_lfps_en(rxx_los_lfps_en),
    .rx0_los_threshold(rxx_los_threshold),
    .rx0_lpd(rxx_lpd),
    .rx0_m(rx0_m),
    .rx0_offcan_cont(rxx_offcan_cont),
    .rx0_p(rx0_p),
    .rx0_pstate(rxx_pstate),
    .rx0_rate(rxx_rate),
    .rx0_ref_ld_val(rxx_ref_ld_val),
    .rx0_req(rx0_req),
    .rx0_reset(rx0_reset),
    .rx0_term_acdc(rxx_term_acdc),
    .rx0_term_en(rxx_term_en),
    .rx0_txmain_dir(rx0_txmain_dir),
    .rx0_txpost_dir(rx0_txpost_dir),
    .rx0_txpre_dir(rx0_txpre_dir),
    .rx0_valid(rx0_valid),
    .rx0_vco_ld_val(rxx_vco_ld_val),
    .rx0_width(rxx_width),
    .rx1_ack(rx1_ack),
    .rx1_adapt_ack(rx1_adapt_ack),
    .rx1_adapt_afe_en(rxx_adapt_afe_en),
    .rx1_adapt_cont(rxx_adapt_cont),
    .rx1_adapt_dfe_en(rxx_adapt_dfe_en),
    .rx1_adapt_fom(rx1_adapt_fom),
    .rx1_adapt_req(rxx_adapt_req),
    .rx1_align_en(rxx_align_en),
    .rx1_cdr_ssc_en(rxx_cdr_ssc_en),
    .rx1_cdr_track_en(rxx_cdr_track_en),
    .rx1_cdr_vco_lowfreq(rxx_cdr_vco_lowfreq),
    .rx1_clk(rx1_clk),
    .rx1_clk_shift(rxx_clk_shift),
    .rx1_data(rx1_data),
    .rx1_data_en(rxx_data_en),
    .rx1_disable(rxx_disable),
    .rx1_div16p5_clk(rx1_div16p5_clk),
    .rx1_div16p5_clk_en(rxx_div16p5_clk_en),
    .rx1_eq_att_lvl(rxx_eq_att_lvl),
    .rx1_eq_ctle_boost(rxx_eq_ctle_boost),
    .rx1_eq_ctle_pole(rxx_eq_ctle_pole),
    .rx1_eq_dfe_tap1(rxx_eq_dfe_tap1),
    .rx1_eq_vga1_gain(rxx_eq_vga1_gain),
    .rx1_eq_vga2_gain(rxx_eq_vga2_gain),
    .rx1_invert(rxx_invert),
    .rx1_los(rx1_los),
    .rx1_los_lfps_en(rxx_los_lfps_en),
    .rx1_los_threshold(rxx_los_threshold),
    .rx1_lpd(rxx_lpd),
    .rx1_m(rx1_m),
    .rx1_offcan_cont(rxx_offcan_cont),
    .rx1_p(rx1_p),
    .rx1_pstate(rxx_pstate),
    .rx1_rate(rxx_rate),
    .rx1_ref_ld_val(rxx_ref_ld_val),
    .rx1_req(rx1_req),
    .rx1_reset(rx1_reset),
    .rx1_term_acdc(rxx_term_acdc),
    .rx1_term_en(rxx_term_en),
    .rx1_txmain_dir(rx1_txmain_dir),
    .rx1_txpost_dir(rx1_txpost_dir),
    .rx1_txpre_dir(rx1_txpre_dir),
    .rx1_valid(rx1_valid),
    .rx1_vco_ld_val(rxx_vco_ld_val),
    .rx1_width(rxx_width),
    .rx2_ack(rx2_ack),
    .rx2_adapt_ack(rx2_adapt_ack),
    .rx2_adapt_afe_en(rxx_adapt_afe_en),
    .rx2_adapt_cont(rxx_adapt_cont),
    .rx2_adapt_dfe_en(rxx_adapt_dfe_en),
    .rx2_adapt_fom(rx2_adapt_fom),
    .rx2_adapt_req(rxx_adapt_req),
    .rx2_align_en(rxx_align_en),
    .rx2_cdr_ssc_en(rxx_cdr_ssc_en),
    .rx2_cdr_track_en(rxx_cdr_track_en),
    .rx2_cdr_vco_lowfreq(rxx_cdr_vco_lowfreq),
    .rx2_clk(rx2_clk),
    .rx2_clk_shift(rxx_clk_shift),
    .rx2_data(rx2_data),
    .rx2_data_en(rxx_data_en),
    .rx2_disable(rxx_disable),
    .rx2_div16p5_clk(rx2_div16p5_clk),
    .rx2_div16p5_clk_en(rxx_div16p5_clk_en),
    .rx2_eq_att_lvl(rxx_eq_att_lvl),
    .rx2_eq_ctle_boost(rxx_eq_ctle_boost),
    .rx2_eq_ctle_pole(rxx_eq_ctle_pole),
    .rx2_eq_dfe_tap1(rxx_eq_dfe_tap1),
    .rx2_eq_vga1_gain(rxx_eq_vga1_gain),
    .rx2_eq_vga2_gain(rxx_eq_vga2_gain),
    .rx2_invert(rxx_invert),
    .rx2_los(rx2_los),
    .rx2_los_lfps_en(rxx_los_lfps_en),
    .rx2_los_threshold(rxx_los_threshold),
    .rx2_lpd(rxx_lpd),
    .rx2_m(rx2_m),
    .rx2_offcan_cont(rxx_offcan_cont),
    .rx2_p(rx2_p),
    .rx2_pstate(rxx_pstate),
    .rx2_rate(rxx_rate),
    .rx2_ref_ld_val(rxx_ref_ld_val),
    .rx2_req(rx2_req),
    .rx2_reset(rx2_reset),
    .rx2_term_acdc(rxx_term_acdc),
    .rx2_term_en(rxx_term_en),
    .rx2_txmain_dir(rx2_txmain_dir),
    .rx2_txpost_dir(rx2_txpost_dir),
    .rx2_txpre_dir(rx2_txpre_dir),
    .rx2_valid(rx2_valid),
    .rx2_vco_ld_val(rxx_vco_ld_val),
    .rx2_width(rxx_width),
    .rx3_ack(rx3_ack),
    .rx3_adapt_ack(rx3_adapt_ack),
    .rx3_adapt_afe_en(rxx_adapt_afe_en),
    .rx3_adapt_cont(rxx_adapt_cont),
    .rx3_adapt_dfe_en(rxx_adapt_dfe_en),
    .rx3_adapt_fom(rx3_adapt_fom),
    .rx3_adapt_req(rxx_adapt_req),
    .rx3_align_en(rxx_align_en),
    .rx3_cdr_ssc_en(rxx_cdr_ssc_en),
    .rx3_cdr_track_en(rxx_cdr_track_en),
    .rx3_cdr_vco_lowfreq(rxx_cdr_vco_lowfreq),
    .rx3_clk(rx3_clk),
    .rx3_clk_shift(rxx_clk_shift),
    .rx3_data(rx3_data),
    .rx3_data_en(rxx_data_en),
    .rx3_disable(rxx_disable),
    .rx3_div16p5_clk(rx3_div16p5_clk),
    .rx3_div16p5_clk_en(rxx_div16p5_clk_en),
    .rx3_eq_att_lvl(rxx_eq_att_lvl),
    .rx3_eq_ctle_boost(rxx_eq_ctle_boost),
    .rx3_eq_ctle_pole(rxx_eq_ctle_pole),
    .rx3_eq_dfe_tap1(rxx_eq_dfe_tap1),
    .rx3_eq_vga1_gain(rxx_eq_vga1_gain),
    .rx3_eq_vga2_gain(rxx_eq_vga2_gain),
    .rx3_invert(rxx_invert),
    .rx3_los(rx3_los),
    .rx3_los_lfps_en(rxx_los_lfps_en),
    .rx3_los_threshold(rxx_los_threshold),
    .rx3_lpd(rxx_lpd),
    .rx3_m(rx3_m),
    .rx3_offcan_cont(rxx_offcan_cont),
    .rx3_p(rx3_p),
    .rx3_pstate(rxx_pstate),
    .rx3_rate(rxx_rate),
    .rx3_ref_ld_val(rxx_ref_ld_val),
    .rx3_req(rx3_req),
    .rx3_reset(rx3_reset),
    .rx3_term_acdc(rxx_term_acdc),
    .rx3_term_en(rxx_term_en),
    .rx3_txmain_dir(rx3_txmain_dir),
    .rx3_txpost_dir(rx3_txpost_dir),
    .rx3_txpre_dir(rx3_txpre_dir),
    .rx3_valid(rx3_valid),
    .rx3_vco_ld_val(rxx_vco_ld_val),
    .rx3_width(rxx_width),
    .rx_vref_ctrl(rx_vref_ctrl),
    .scan_cr_clk(scan_cr_clk),
    .scan_cr_in(scan_cr_in),
    .scan_cr_out(scan_cr_out),
    .scan_mode(scan_mode),
    .scan_mplla_div16p5_clk(scan_mplla_div16p5_clk),
    .scan_mplla_div16p5_in(scan_mplla_div16p5_in),
    .scan_mplla_div16p5_out(scan_mplla_div16p5_out),
    .scan_mplla_div33_clk(scan_mplla_div33_clk),
    .scan_mplla_div66_clk(scan_mplla_div66_clk),
    .scan_mplla_div_clk(scan_mplla_div_clk),
    .scan_mplla_div_in(scan_mplla_div_in),
    .scan_mplla_div_out(scan_mplla_div_out),
    .scan_mplla_dword_clk(scan_mplla_dword_clk),
    .scan_mplla_dword_in(scan_mplla_dword_in),
    .scan_mplla_dword_out(scan_mplla_dword_out),
    .scan_mplla_fb_clk(scan_mplla_fb_clk),
    .scan_mplla_fb_in(scan_mplla_fb_in),
    .scan_mplla_fb_out(scan_mplla_fb_out),
    .scan_mplla_oword_clk(scan_mplla_oword_clk),
    .scan_mplla_qword_clk(scan_mplla_qword_clk),
    .scan_mplla_qword_in(scan_mplla_qword_in),
    .scan_mplla_qword_out(scan_mplla_qword_out),
    .scan_mplla_ref_clk(scan_mplla_ref_clk),
    .scan_mplla_ref_in(scan_mplla_ref_in),
    .scan_mplla_ref_out(scan_mplla_ref_out),
    .scan_mplla_ssc_clk(scan_mplla_ssc_clk),
    .scan_mplla_ssc_in(scan_mplla_ssc_in),
    .scan_mplla_ssc_out(scan_mplla_ssc_out),
    .scan_mplla_word_clk(scan_mplla_word_clk),
    .scan_mplla_word_in(scan_mplla_word_in),
    .scan_mplla_word_out(scan_mplla_word_out),
    .scan_mpllb_div_clk(scan_mpllb_div_clk),
    .scan_mpllb_div_in(scan_mpllb_div_in),
    .scan_mpllb_div_out(scan_mpllb_div_out),
    .scan_mpllb_dword_clk(scan_mpllb_dword_clk),
    .scan_mpllb_dword_in(scan_mpllb_dword_in),
    .scan_mpllb_dword_out(scan_mpllb_dword_out),
    .scan_mpllb_fb_clk(scan_mpllb_fb_clk),
    .scan_mpllb_fb_in(scan_mpllb_fb_in),
    .scan_mpllb_fb_out(scan_mpllb_fb_out),
    .scan_mpllb_oword_clk(scan_mpllb_oword_clk),
    .scan_mpllb_qword_clk(scan_mpllb_qword_clk),
    .scan_mpllb_qword_in(scan_mpllb_qword_in),
    .scan_mpllb_qword_out(scan_mpllb_qword_out),
    .scan_mpllb_ref_clk(scan_mpllb_ref_clk),
    .scan_mpllb_ref_in(scan_mpllb_ref_in),
    .scan_mpllb_ref_out(scan_mpllb_ref_out),
    .scan_mpllb_ssc_clk(scan_mpllb_ssc_clk),
    .scan_mpllb_ssc_in(scan_mpllb_ssc_in),
    .scan_mpllb_ssc_out(scan_mpllb_ssc_out),
    .scan_mpllb_word_clk(scan_mpllb_word_clk),
    .scan_mpllb_word_in(scan_mpllb_word_in),
    .scan_mpllb_word_out(scan_mpllb_word_out),
    .scan_ref_clk(scan_ref_clk),
    .scan_ref_dig_clk(scan_ref_dig_clk),
    .scan_ref_dig_in(scan_ref_dig_in),
    .scan_ref_dig_out(scan_ref_dig_out),
    .scan_ref_in(scan_ref_in),
    .scan_ref_out(scan_ref_out),
    .scan_ref_range_clk(scan_ref_range_clk),
    .scan_ref_range_in(scan_ref_range_in),
    .scan_ref_range_out(scan_ref_range_out),
    .scan_rx0_adpt_clk(scan_rx0_adpt_clk),
    .scan_rx0_adpt_in(scan_rx0_adpt_in),
    .scan_rx0_adpt_out(scan_rx0_adpt_out),
    .scan_rx0_asic_clk(scan_rx0_asic_clk),
    .scan_rx0_asic_in(scan_rx0_asic_in),
    .scan_rx0_asic_out(scan_rx0_asic_out),
    .scan_rx0_div16p5_clk(scan_rx0_div16p5_clk),
    .scan_rx0_div16p5_in(scan_rx0_div16p5_in),
    .scan_rx0_div16p5_out(scan_rx0_div16p5_out),
    .scan_rx0_dpll_clk(scan_rx0_dpll_clk),
    .scan_rx0_dpll_in(scan_rx0_dpll_in),
    .scan_rx0_dpll_out(scan_rx0_dpll_out),
    .scan_rx0_dword_clk(scan_rx0_dword_clk),
    .scan_rx0_dword_in(scan_rx0_dword_in),
    .scan_rx0_dword_out(scan_rx0_dword_out),
    .scan_rx0_scope_clk(scan_rx0_scope_clk),
    .scan_rx0_scope_in(scan_rx0_scope_in),
    .scan_rx0_scope_out(scan_rx0_scope_out),
    .scan_rx0_stat_clk(scan_rx0_stat_clk),
    .scan_rx0_stat_in(scan_rx0_stat_in),
    .scan_rx0_stat_out(scan_rx0_stat_out),
    .scan_rx0_word_clk(scan_rx0_word_clk),
    .scan_rx0_word_in(scan_rx0_word_in),
    .scan_rx0_word_out(scan_rx0_word_out),
    .scan_rx1_adpt_clk(scan_rx1_adpt_clk),
    .scan_rx1_adpt_in(scan_rx1_adpt_in),
    .scan_rx1_adpt_out(scan_rx1_adpt_out),
    .scan_rx1_asic_clk(scan_rx1_asic_clk),
    .scan_rx1_asic_in(scan_rx1_asic_in),
    .scan_rx1_asic_out(scan_rx1_asic_out),
    .scan_rx1_div16p5_clk(scan_rx1_div16p5_clk),
    .scan_rx1_div16p5_in(scan_rx1_div16p5_in),
    .scan_rx1_div16p5_out(scan_rx1_div16p5_out),
    .scan_rx1_dpll_clk(scan_rx1_dpll_clk),
    .scan_rx1_dpll_in(scan_rx1_dpll_in),
    .scan_rx1_dpll_out(scan_rx1_dpll_out),
    .scan_rx1_dword_clk(scan_rx1_dword_clk),
    .scan_rx1_dword_in(scan_rx1_dword_in),
    .scan_rx1_dword_out(scan_rx1_dword_out),
    .scan_rx1_scope_clk(scan_rx1_scope_clk),
    .scan_rx1_scope_in(scan_rx1_scope_in),
    .scan_rx1_scope_out(scan_rx1_scope_out),
    .scan_rx1_stat_clk(scan_rx1_stat_clk),
    .scan_rx1_stat_in(scan_rx1_stat_in),
    .scan_rx1_stat_out(scan_rx1_stat_out),
    .scan_rx1_word_clk(scan_rx1_word_clk),
    .scan_rx1_word_in(scan_rx1_word_in),
    .scan_rx1_word_out(scan_rx1_word_out),
    .scan_rx2_adpt_clk(scan_rx2_adpt_clk),
    .scan_rx2_adpt_in(scan_rx2_adpt_in),
    .scan_rx2_adpt_out(scan_rx2_adpt_out),
    .scan_rx2_asic_clk(scan_rx2_asic_clk),
    .scan_rx2_asic_in(scan_rx2_asic_in),
    .scan_rx2_asic_out(scan_rx2_asic_out),
    .scan_rx2_div16p5_clk(scan_rx2_div16p5_clk),
    .scan_rx2_div16p5_in(scan_rx2_div16p5_in),
    .scan_rx2_div16p5_out(scan_rx2_div16p5_out),
    .scan_rx2_dpll_clk(scan_rx2_dpll_clk),
    .scan_rx2_dpll_in(scan_rx2_dpll_in),
    .scan_rx2_dpll_out(scan_rx2_dpll_out),
    .scan_rx2_dword_clk(scan_rx2_dword_clk),
    .scan_rx2_dword_in(scan_rx2_dword_in),
    .scan_rx2_dword_out(scan_rx2_dword_out),
    .scan_rx2_scope_clk(scan_rx2_scope_clk),
    .scan_rx2_scope_in(scan_rx2_scope_in),
    .scan_rx2_scope_out(scan_rx2_scope_out),
    .scan_rx2_stat_clk(scan_rx2_stat_clk),
    .scan_rx2_stat_in(scan_rx2_stat_in),
    .scan_rx2_stat_out(scan_rx2_stat_out),
    .scan_rx2_word_clk(scan_rx2_word_clk),
    .scan_rx2_word_in(scan_rx2_word_in),
    .scan_rx2_word_out(scan_rx2_word_out),
    .scan_rx3_adpt_clk(scan_rx3_adpt_clk),
    .scan_rx3_adpt_in(scan_rx3_adpt_in),
    .scan_rx3_adpt_out(scan_rx3_adpt_out),
    .scan_rx3_asic_clk(scan_rx3_asic_clk),
    .scan_rx3_asic_in(scan_rx3_asic_in),
    .scan_rx3_asic_out(scan_rx3_asic_out),
    .scan_rx3_div16p5_clk(scan_rx3_div16p5_clk),
    .scan_rx3_div16p5_in(scan_rx3_div16p5_in),
    .scan_rx3_div16p5_out(scan_rx3_div16p5_out),
    .scan_rx3_dpll_clk(scan_rx3_dpll_clk),
    .scan_rx3_dpll_in(scan_rx3_dpll_in),
    .scan_rx3_dpll_out(scan_rx3_dpll_out),
    .scan_rx3_dword_clk(scan_rx3_dword_clk),
    .scan_rx3_dword_in(scan_rx3_dword_in),
    .scan_rx3_dword_out(scan_rx3_dword_out),
    .scan_rx3_scope_clk(scan_rx3_scope_clk),
    .scan_rx3_scope_in(scan_rx3_scope_in),
    .scan_rx3_scope_out(scan_rx3_scope_out),
    .scan_rx3_stat_clk(scan_rx3_stat_clk),
    .scan_rx3_stat_in(scan_rx3_stat_in),
    .scan_rx3_stat_out(scan_rx3_stat_out),
    .scan_rx3_word_clk(scan_rx3_word_clk),
    .scan_rx3_word_in(scan_rx3_word_in),
    .scan_rx3_word_out(scan_rx3_word_out),
    .scan_set_rst(scan_set_rst),
    .scan_shift(scan_shift),
    .scan_shift_cg(scan_shift_cg),
    .scan_tx0_ana_dword_clk(scan_tx0_ana_dword_clk),
    .scan_tx0_ana_dword_in(scan_tx0_ana_dword_in),
    .scan_tx0_ana_dword_out(scan_tx0_ana_dword_out),
    .scan_tx0_ana_word_clk(scan_tx0_ana_word_clk),
    .scan_tx0_ana_word_in(scan_tx0_ana_word_in),
    .scan_tx0_ana_word_out(scan_tx0_ana_word_out),
    .scan_tx0_asic_dword_clk(scan_tx0_asic_dword_clk),
    .scan_tx0_asic_dword_in(scan_tx0_asic_dword_in),
    .scan_tx0_asic_dword_out(scan_tx0_asic_dword_out),
    .scan_tx0_in(scan_tx0_in),
    .scan_tx0_out(scan_tx0_out),
    .scan_tx1_ana_dword_clk(scan_tx1_ana_dword_clk),
    .scan_tx1_ana_dword_in(scan_tx1_ana_dword_in),
    .scan_tx1_ana_dword_out(scan_tx1_ana_dword_out),
    .scan_tx1_ana_word_clk(scan_tx1_ana_word_clk),
    .scan_tx1_ana_word_in(scan_tx1_ana_word_in),
    .scan_tx1_ana_word_out(scan_tx1_ana_word_out),
    .scan_tx1_asic_dword_clk(scan_tx1_asic_dword_clk),
    .scan_tx1_asic_dword_in(scan_tx1_asic_dword_in),
    .scan_tx1_asic_dword_out(scan_tx1_asic_dword_out),
    .scan_tx1_in(scan_tx1_in),
    .scan_tx1_out(scan_tx1_out),
    .scan_tx2_ana_dword_clk(scan_tx2_ana_dword_clk),
    .scan_tx2_ana_dword_in(scan_tx2_ana_dword_in),
    .scan_tx2_ana_dword_out(scan_tx2_ana_dword_out),
    .scan_tx2_ana_word_clk(scan_tx2_ana_word_clk),
    .scan_tx2_ana_word_in(scan_tx2_ana_word_in),
    .scan_tx2_ana_word_out(scan_tx2_ana_word_out),
    .scan_tx2_asic_dword_clk(scan_tx2_asic_dword_clk),
    .scan_tx2_asic_dword_in(scan_tx2_asic_dword_in),
    .scan_tx2_asic_dword_out(scan_tx2_asic_dword_out),
    .scan_tx2_in(scan_tx2_in),
    .scan_tx2_out(scan_tx2_out),
    .scan_tx3_ana_dword_clk(scan_tx3_ana_dword_clk),
    .scan_tx3_ana_dword_in(scan_tx3_ana_dword_in),
    .scan_tx3_ana_dword_out(scan_tx3_ana_dword_out),
    .scan_tx3_ana_word_clk(scan_tx3_ana_word_clk),
    .scan_tx3_ana_word_in(scan_tx3_ana_word_in),
    .scan_tx3_ana_word_out(scan_tx3_ana_word_out),
    .scan_tx3_asic_dword_clk(scan_tx3_asic_dword_clk),
    .scan_tx3_asic_dword_in(scan_tx3_asic_dword_in),
    .scan_tx3_asic_dword_out(scan_tx3_asic_dword_out),
    .scan_tx3_in(scan_tx3_in),
    .scan_tx3_out(scan_tx3_out),
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_addr(sram_addr),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_bypass(sram_bypass),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_clk(sram_clk),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_ext_ld_done(sram_ext_ld_done),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_init_done(sram_init_done),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_rd_data(sram_rd_data),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_rd_en(sram_rd_en),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_wr_data(sram_wr_data),
`endif
`ifdef DWC_E12MP_X4NS_SRAM_SUPPORT
    .sram_wr_en(sram_wr_en),
`endif
    .test_burnin(test_burnin),
    .test_powerdown(test_powerdown),
    .tx0_ack(tx0_ack),
    .tx0_beacon_en(txx_beacon_en),
    .tx0_clk(tx0_clk),
    .tx0_clk_rdy(tx0_clk_rdy),
    .tx0_data(tx0_data),
    .tx0_data_en(txx_data_en),
    .tx0_detrx_req(txx_detrx_req),
    .tx0_detrx_result(tx0_detrx_result),
    .tx0_disable(txx_disable),
    .tx0_eq_main(txx_eq_main),
    .tx0_eq_post(txx_eq_post),
    .tx0_eq_pre(txx_eq_pre),
    .tx0_iboost_lvl(txx_iboost_lvl),
    .tx0_invert(txx_invert),
    .tx0_lpd(txx_lpd),
    .tx0_m(tx0_m),
    .tx0_master_mplla_state(tx0_master_mplla_state),
    .tx0_master_mpllb_state(tx0_master_mpllb_state),
    .tx0_mpll_en(txx_mpll_en),
    .tx0_mpllb_sel(txx_mpllb_sel),
    .tx0_p(tx0_p),
    .tx0_pstate(txx_pstate),
    .tx0_rate(txx_rate),
    .tx0_req(tx0_req),
    .tx0_reset(tx0_reset),
    .tx0_vboost_en(txx_vboost_en),
    .tx0_width(txx_width),
    .tx0_word_clk(tx0_word_clk),
    .tx1_ack(tx1_ack),
    .tx1_beacon_en(txx_beacon_en),
    .tx1_clk(tx1_clk),
    .tx1_clk_rdy(tx1_clk_rdy),
    .tx1_data(tx1_data),
    .tx1_data_en(txx_data_en),
    .tx1_detrx_req(txx_detrx_req),
    .tx1_detrx_result(tx1_detrx_result),
    .tx1_disable(txx_disable),
    .tx1_eq_main(txx_eq_main),
    .tx1_eq_post(txx_eq_post),
    .tx1_eq_pre(txx_eq_pre),
    .tx1_iboost_lvl(txx_iboost_lvl),
    .tx1_invert(txx_invert),
    .tx1_lpd(txx_lpd),
    .tx1_m(tx1_m),
    .tx1_master_mplla_state(tx1_master_mplla_state),
    .tx1_master_mpllb_state(tx1_master_mpllb_state),
    .tx1_mpll_en(txx_mpll_en),
    .tx1_mpllb_sel(txx_mpllb_sel),
    .tx1_p(tx1_p),
    .tx1_pstate(txx_pstate),
    .tx1_rate(txx_rate),
    .tx1_req(tx1_req),
    .tx1_reset(tx1_reset),
    .tx1_vboost_en(txx_vboost_en),
    .tx1_width(txx_width),
    .tx1_word_clk(tx1_word_clk),
    .tx2_ack(tx2_ack),
    .tx2_beacon_en(txx_beacon_en),
    .tx2_clk(tx2_clk),
    .tx2_clk_rdy(tx2_clk_rdy),
    .tx2_data(tx2_data),
    .tx2_data_en(txx_data_en),
    .tx2_detrx_req(txx_detrx_req),
    .tx2_detrx_result(tx2_detrx_result),
    .tx2_disable(txx_disable),
    .tx2_eq_main(txx_eq_main),
    .tx2_eq_post(txx_eq_post),
    .tx2_eq_pre(txx_eq_pre),
    .tx2_iboost_lvl(txx_iboost_lvl),
    .tx2_invert(txx_invert),
    .tx2_lpd(txx_lpd),
    .tx2_m(tx2_m),
    .tx2_master_mplla_state(tx2_master_mplla_state),
    .tx2_master_mpllb_state(tx2_master_mpllb_state),
    .tx2_mpll_en(txx_mpll_en),
    .tx2_mpllb_sel(txx_mpllb_sel),
    .tx2_p(tx2_p),
    .tx2_pstate(txx_pstate),
    .tx2_rate(txx_rate),
    .tx2_req(tx2_req),
    .tx2_reset(tx2_reset),
    .tx2_vboost_en(txx_vboost_en),
    .tx2_width(txx_width),
    .tx2_word_clk(tx2_word_clk),
    .tx3_ack(tx3_ack),
    .tx3_beacon_en(txx_beacon_en),
    .tx3_clk(tx3_clk),
    .tx3_clk_rdy(tx3_clk_rdy),
    .tx3_data(tx3_data),
    .tx3_data_en(txx_data_en),
    .tx3_detrx_req(txx_detrx_req),
    .tx3_detrx_result(tx3_detrx_result),
    .tx3_disable(txx_disable),
    .tx3_eq_main(txx_eq_main),
    .tx3_eq_post(txx_eq_post),
    .tx3_eq_pre(txx_eq_pre),
    .tx3_iboost_lvl(txx_iboost_lvl),
    .tx3_invert(txx_invert),
    .tx3_lpd(txx_lpd),
    .tx3_m(tx3_m),
    .tx3_master_mplla_state(tx3_master_mplla_state),
    .tx3_master_mpllb_state(tx3_master_mpllb_state),
    .tx3_mpll_en(txx_mpll_en),
    .tx3_mpllb_sel(txx_mpllb_sel),
    .tx3_p(tx3_p),
    .tx3_pstate(txx_pstate),
    .tx3_rate(txx_rate),
    .tx3_req(tx3_req),
    .tx3_reset(tx3_reset),
    .tx3_vboost_en(txx_vboost_en),
    .tx3_width(txx_width),
    .tx3_word_clk(tx3_word_clk),
    .tx_vboost_lvl(tx_vboost_lvl)
  );



mtip_top_10_40_mac_pcs UUT (

    .reset_reg_clk(         reset_reg_clk_in           ),
    .mac_reset_ref_clk(     mac_reset_ref_clk_in       ),
    .mac_reset_ff_rx_clk(   mac_reset_ff_rx_clk_in     ),
    .mac_reset_ff_tx_clk(   mac_reset_ff_tx_clk_in     ),
    .xlaui_reset_rx_clk(    xlaui_reset_rx_clk_in[3:0] ),
    .xlaui_reset_tx_clk(    xlaui_reset_tx_clk_in      ),
    .xlaui_reset_ref_clk(   xlaui_reset_ref_clk_in     ),
    .xaui_reset_rx_clk(     xaui_reset_rx_clk_in[3:0]  ),
    .xaui_reset_tx_clk(     xaui_reset_tx_clk_in       ),
    .reg_clk(               reg_clk               ),
    .ref_clk(               ref_clk               ),
    .rx_clk(                {sd3_rx_clk, sd2_rx_clk, sd1_rx_clk, sd0_rx_clk}),
    // .rx_clk(                {sd0_rx_clk, sd1_rx_clk, sd2_rx_clk, sd3_rx_clk}),
    .tx_clk(                sd_tx_clk       ),
    .ff_rx_clk(             ff_clk                ),
    .ff_tx_clk(             ff_clk                ),
    .sd0_tx(                sd0_tx                ),
    .sd1_tx(                sd1_tx                ),
    .sd2_tx(                sd2_tx                ),
    .sd3_tx(                sd3_tx                ),      
    .sd0_rx(                sd0_rx                ),
    .sd1_rx(                sd1_rx                ),
    .sd2_rx(                sd2_rx                ),
    .sd3_rx(                sd3_rx                ),  
    .sd_signal(             {signal_det0, signal_det1, signal_det2, signal_det3}), 
    .axi_ttvalid(           axi_ttvalid           ),
    .axi_ttlast(            axi_ttlast            ),
    .axi_ttkeep(            axi_ttkeep            ),
    .axi_ttdata(            axi_ttdata            ),
    .axi_ttuser(            axi_ttuser            ), 
    .axi_ttready(           axi_ttready           ),
    .axi_rtvalid(           axi_rtvalid           ),
    .axi_rtlast(            axi_rtlast            ),
    .axi_rtkeep(            axi_rtkeep            ),
    .axi_rtdata(            axi_rtdata            ),
    .axi_rtuser(            axi_rtuser            ),
    .axi_rtready(           axi_rtready           ),
    .tx_ovr_err(            ),
    .tx_underflow(          ),
    .tx_empty(              ),
    .ff_rx_empty(           ),
    .ena_40g(               pcs_40Geth_ena        ),
    .jumbo_en(              1'b1                  ),
    .lpi_txhold(            mac_lpi_txhold        ),
    .loc_fault(             mac_loc_fault         ),
    .rem_fault(             mac_rem_fault         ),
    .li_fault(              mac_li_fault          ),
    .tx_loc_fault(          mac_tx_loc_fault      ),
    .tx_rem_fault(          mac_tx_rem_fault      ),
    .tx_li_fault(           mac_tx_li_fault       ),
    .phy_txena(             ),
    .loop_ena(              ),
    .pfc_mode(              mac_pfc_mode    ),
    .pause_on(              mac_pause_on    ),
    .xoff_gen(              mac_xoff_gen    ),
    .tx_sfd_o(              ),
    .frc_in_tx(             mac_frc_in_tx   ),
    .rx_sfd_o(              ),
    .frc_in_rx(             mac_frc_in_rx   ),
    .xgmii_rx_sop_shift(    ),
    .xgmii_tx_sop_shift(    ),
    .tx_ts_val(             mac_tx_ts_val   ),
    .tx_ts(                 mac_tx_ts       ),
    .tx_ts_id(              mac_tx_ts_id    ),
    .tx_ts_frm_out(         ),
    .x_align_done(          x_align_done    ),
    .x_disp_err(            x_disp_err      ),
    .x_char_err(            x_char_err      ),
    .x_cg_align(            x_cg_align      ),
    .x_sync(                x_sync          ),
    .x_pat(                 x_pat           ),
    .xl_ber_timer_done(     xl_ber_timer_done),
    .xl_block_lock(         xl_block_lock   ),
    .xl_align_done(         xl_align_done   ),
    .xl_hi_ber(             xl_hi_ber       ),
    .regm_wren(             mac_reg_wren    ),
    .regm_rden(             mac_reg_rden    ),
    .regm_addr(             mac_reg_addr    ),
    .regm_din(              mac_reg_din     ),
    .regm_dout(             mac_reg_dout    ),
    .regm_busy(             mac_reg_busy    ),
    .regm_ts_avail(         ),
    .regm_lowp(             ),
    .regm_lowp_ena(         mac_reg_lowp_ena),
    .regxl_rden(            xlpcs_reg_rden  ),
    .regxl_wren(            xlpcs_reg_wren  ),
    .regxl_addr(            xlpcs_reg_addr  ),
    .regxl_din(             xlpcs_reg_din   ),
    .regxl_dout(            xlpcs_reg_dout  ),
    .regxl_busy(            xlpcs_reg_busy  ),
    .regx_rden(             xpcs_reg_rden   ),
    .regx_wren(             xpcs_reg_wren   ),
    .regx_addr(             xpcs_reg_addr   ),
    .regx_din(              xpcs_reg_din    ),
    .regx_dout(             xpcs_reg_dout   ),
    .regx_busy(             xpcs_reg_busy   ),
    .mdc(                                   ),
    .mdio_in(               1'b0            ),
    .mdio_out(                              ),
    .mdio_oen(                              ),
    .rstm_raddr(            rstm_raddr            ),
    .rstm_rden(             rstm_rden             ),
    .rstm_rdata(            rstm_rdata            ),
    .rstm_wren(             rstm_wren             ),
    .rstm_waddr(            rstm_waddr            ),
    .rstm_wdata(            rstm_wdata            ),
    .tstm_raddr(            tstm_raddr            ),
    .tstm_rden(             tstm_rden             ),
    .tstm_rdata(            tstm_rdata            ),
    .tstm_wren(             tstm_wren             ),
    .tstm_waddr(            tstm_waddr            ),
    .tstm_wdata(            tstm_wdata            ),
    .rxd_raddr(             rxd_raddr             ),
    .rxd_rden(              rxd_rden              ),
    .rxd_rdata(             rxd_rdata             ),
    .rxd_recc(              rxd_recc              ),
    .rxd_wren(              rxd_wren              ),
    .rxd_waddr(             rxd_waddr             ),
    .rxd_wdata(             rxd_wdata             ),
    .rxs_raddr(             rxs_raddr             ),
    .rxs_rden(              rxs_rden              ),
    .rxs_rdata(             rxs_rdata             ),
    .rxs_wren(              rxs_wren              ),
    .rxs_waddr(             rxs_waddr             ),
    .rxs_wdata(             rxs_wdata             ),
    .rxp_raddr(             rxp_raddr             ),
    .rxp_rden(              rxp_rden              ),
    .rxp_rdata(             rxp_rdata             ),
    .rxp_wren(              rxp_wren              ),
    .rxp_waddr(             rxp_waddr             ),
    .rxp_wdata(             rxp_wdata             ),
    .txd_raddr(             txd_raddr             ),
    .txd_rden(              txd_rden              ),
    .txd_rdata(             txd_rdata             ),
    .txd_recc(              txd_recc              ),
    .txd_wren(              txd_wren              ),
    .txd_waddr(             txd_waddr             ),
    .txd_wdata(             txd_wdata             ),
    .txs_raddr(             txs_raddr             ),
    .txs_rden(              txs_rden              ),
    .txs_rdata(             txs_rdata             ),
    .txs_wren(              txs_wren              ),
    .txs_waddr(             txs_waddr             ),
    .txs_wdata(             txs_wdata             ));

//  CLK_MUX

//tx_clk select for PHY
clk_mux2 tx0_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (mplla_word_clk     ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (tx0_clk            )
    );
clk_mux2 tx1_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (mplla_word_clk     ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (tx1_clk            )
    );
clk_mux2 tx2_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (mplla_word_clk     ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (tx2_clk            )
    );
clk_mux2 tx3_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (mplla_word_clk     ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (tx3_clk            )
    );

//MAC_PCS clk select
//40G: ref_clk >= 630MHz    ff_clk >= 630MHz
//10G: ref_clk >= 156.25MHz     ff >= 156.25MHz
clk_mux2 ref_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (ref_ff_clk_630plus ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (ref_clk            )
    );
clk_mux2 ff_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (ref_ff_clk_630plus ),
    .clk_sel    (lane_40Geth_ena    ),
    .clk_out    (ff_clk             )
    );
// clk_mux2 reg_clk_mux2(
//     .clk_in0    (phy_ref_dig_clk    ),
//     .clk_in1    (1'd0               ),
//     .clk_sel    (1'd0               ),
//     .clk_out    (reg_clk            )
//     );
//sd_tx_clk select for PCS
clk_mux2 sd_tx_clk_mux2(
    .clk_in0    (mpllb_qword_clk    ),
    .clk_in1    (mplla_word_clk     ),
    .clk_sel    (pcs_40Geth_ena     ),
    .clk_out    (sd_tx_clk          )
    );

//sd_rx_clk select for PCS (Loopback)
clk_mux2 sd0_rx_clk_mux2(
    .clk_in0    (rx0_clk            ),
    .clk_in1    (sd_tx_clk          ),
    .clk_sel    (sd_tx2rx_par_lb_en ),
    .clk_out    (sd0_rx_clk         )
    );
clk_mux2 sd1_rx_clk_mux2(
    .clk_in0    (rx1_clk            ),
    .clk_in1    (sd_tx_clk          ),
    .clk_sel    (sd_tx2rx_par_lb_en ),
    .clk_out    (sd1_rx_clk         )
    );
clk_mux2 sd2_rx_clk_mux2(
    .clk_in0    (rx2_clk            ),
    .clk_in1    (sd_tx_clk          ),
    .clk_sel    (sd_tx2rx_par_lb_en ),
    .clk_out    (sd2_rx_clk         )
    );
clk_mux2 sd3_rx_clk_mux2(
    .clk_in0    (rx3_clk            ),
    .clk_in1    (sd_tx_clk          ),
    .clk_sel    (sd_tx2rx_par_lb_en ),
    .clk_out    (sd3_rx_clk         )
    );
  // MAC Statistics
  // --------------

sdpm_gen #(65, 64, 6) U_RXSTAT (
    .wad    (rstm_waddr),
    .din    (rstm_wdata),
    .wclk   (ref_clk),
    .rclk   (ref_clk),
    .wren   (rstm_wren),
    .rden   (rstm_rden),
    .rad    (rstm_raddr),
    .dout   (rstm_rdata));
sdpm_gen #(65, 64, 6) U_TXSTAT (
    .wad    (tstm_waddr),
    .din    (tstm_wdata),
    .wclk   (ref_clk),
    .rclk   (ref_clk),
    .wren   (tstm_wren),
    .rden   (tstm_rden),
    .rad    (tstm_raddr),
    .dout   (tstm_rdata));

// ram_dp_d64_w65_wrapper U_RXSTAT(
//     .clka  ( ref_clk  ),
//     .clkb  ( ref_clk  ),
//     .wea   ( 1'b0   ),
//     .web   ( 1'b1   ),
//     .addra ( rstm_waddr ),
//     .addrb ( rstm_raddr ),
//     .dina  ( rstm_wdata ),
//     .dinb  ( 65'b0  ),
//     .douta ( ),
//     .doutb ( rstm_rdata ) ,
//     .ram_dp_cfg_register(ram_dp_cfg_register),
//     .cena(rstm_wren) ,
//     .cenb(rstm_rden) 
// );
// ram_dp_d64_w65_wrapper  U_TXSTAT(
//     .clka  ( ref_clk  ),
//     .clkb  ( ref_clk  ),
//     .wea   ( 1'b0   ),
//     .web   ( 1'b1   ),
//     .addra ( tstm_waddr ),
//     .addrb ( tstm_raddr ),
//     .dina  ( tstm_wdata ),
//     .dinb  ( 65'b0  ),
//     .douta ( ),
//     .doutb ( tstm_rdata ) ,
//     .ram_dp_cfg_register(ram_dp_cfg_register),
//     .cena(tstm_wren) ,
//     .cenb(tstm_rden) 
// );

// MAC FIFOs
sdpm_gen #(66, 32, 5) U_MAC_TXD (
    .wad    (txd_waddr),
    .din    (txd_wdata),
    .wclk   (ff_clk),
    .rclk   (ref_clk),
    .wren   (txd_wren),
    .rden   (txd_rden),
    .rad    (txd_raddr),
    .dout   (txd_rdata));

// rf_2p_d32_w66_wrapper U_MAC_TXD(
//     .clka(ref_clk),
//     .wren(txd_wren),
//     .waddr(txd_waddr),
//     .wdata(txd_wdata),
//     .clkb(ff_clk),
//     .rden(txd_rden),
//     .raddr(txd_raddr),
//     .rdata(txd_rdata),
//     .rf_2p_cfg_register(rf_2p_cfg_register)
// );

assign txd_recc = 1'b0; 

sdpm_gen #(23, 32, 5) U_MAC_TXS (
    .wad    (txs_waddr),
    .din    (txs_wdata),
    .wclk   (ff_clk),
    .rclk   (ref_clk),
    .wren   (txs_wren),
    .rden   (txs_rden),
    .rad    (txs_raddr),
    .dout   (txs_rdata));

assign mac_txd_recc = 1'b0;

sdpm_gen #(64,32,5) U_MAC_RXD (
    .wad    (rxd_waddr),
    .din    (rxd_wdata),
    .wclk   (ref_clk),
    .rclk   (ff_clk),
    .wren   (rxd_wren),
    .rden   (rxd_rden),
    .rad    (rxd_raddr),
    .dout   (rxd_rdata));

// rf_2p_d32_w64_wrapper U_MAC_RXD(
//     .clka(ff_clk),
//     .wren(rxd_wren),
//     .waddr(rxd_waddr),
//     .wdata(rxd_wdata),
//     .clkb(ref_clk),
//     .rden(rxd_rden),
//     .raddr(rxd_raddr),
//     .rdata(rxd_rdata),
//     .rf_2p_cfg_register(rf_2p_cfg_register)
// );

assign rxd_recc = 1'b0; 

sdpm_gen #(42,32,5) U_MAC_RXS (
    .wad    (rxs_waddr),
    .din    (rxs_wdata),
    .wclk   (ref_clk),
    .rclk   (ff_clk),
    .wren   (rxs_wren),
    .rden   (rxs_rden),
    .rad    (rxs_raddr),
    .dout   (rxs_rdata));

// rf_2p_d32_w42_wrapper U_MAC_RXS(
//     .clka(ff_clk),
//     .wren(rxs_wren),
//     .waddr(rxs_waddr),
//     .wdata(rxs_wdata),
//     .clkb(ref_clk),
//     .rden(rxs_rden),
//     .raddr(rxs_raddr),
//     .rdata(rxs_rdata),
//     .rf_2p_cfg_register(rf_2p_cfg_register)
// );


sdpm_gen #(64,32,5) U_MAC_RXP (
    .wad    (rxp_waddr),
    .din    (rxp_wdata),
    .wclk   (ref_clk),
    .rclk   (ff_clk),
    .wren   (rxp_wren),
    .rden   (rxp_rden),
    .rad    (rxp_raddr),
    .dout   (rxp_rdata));

// rf_2p_d32_w64_wrapper U_MAC_RXP(
//     .clka(ff_clk),
//     .wren(rxp_wren),
//     .waddr(rxp_waddr),
//     .wdata(rxp_wdata),
//     .clkb(ref_clk),
//     .rden(rxp_rden),
//     .raddr(rxp_raddr),
//     .rdata(rxp_rdata),
//     .rf_2p_cfg_register(rf_2p_cfg_register)
// );

//reset_sync
hdfwd_rstp_sync reset_reg_clk_sync ( reset_reg_clk_in, reg_clk, reset_reg_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync reset_ref_clk_sync ( mac_reset_ref_clk_in, ref_clk, mac_reset_ref_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync mac_reset_ff_rx_clk_sync ( mac_reset_ff_rx_clk_in, ff_clk, mac_reset_ff_rx_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync mac_reset_ff_tx_clk_sync ( mac_reset_ff_tx_clk_in, ff_clk, mac_reset_ff_tx_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_rx_clk0_sync ( xlaui_reset_rx_clk_in[0], sd0_rx_clk, xlaui_reset_rx_clk_temp[0], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_rx_clk1_sync ( xlaui_reset_rx_clk_in[1], sd1_rx_clk, xlaui_reset_rx_clk_temp[1], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_rx_clk2_sync ( xlaui_reset_rx_clk_in[2], sd2_rx_clk, xlaui_reset_rx_clk_temp[2], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_rx_clk3_sync ( xlaui_reset_rx_clk_in[3], sd3_rx_clk, xlaui_reset_rx_clk_temp[3], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_tx_clk_sync ( xlaui_reset_tx_clk_in, sd_tx_clk, xlaui_reset_tx_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xlaui_reset_ref_clk_sync ( xlaui_reset_ref_clk_in, ref_clk, xlaui_reset_ref_clk_temp, mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xaui_reset_rx_clk0_sync ( xaui_reset_rx_clk_in[0], sd0_rx_clk, xaui_reset_rx_clk_temp[0], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xaui_reset_rx_clk1_sync ( xaui_reset_rx_clk_in[1], sd1_rx_clk, xaui_reset_rx_clk_temp[1], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xaui_reset_rx_clk2_sync ( xaui_reset_rx_clk_in[2], sd2_rx_clk, xaui_reset_rx_clk_temp[2], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xaui_reset_rx_clk3_sync ( xaui_reset_rx_clk_in[3], sd3_rx_clk, xaui_reset_rx_clk_temp[3], mac_reset, scan_mode, 1'b0 );
hdfwd_rstp_sync xaui_reset_tx_clk_sync ( xaui_reset_tx_clk_in, sd_tx_clk, xaui_reset_tx_clk_temp, mac_reset, scan_mode, 1'b0 );

// mac_reset_sync reset_reg_clk_sync(
//     .d_clk(reg_clk),
//     .rst_i(reset_reg_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(reset_reg_clk_in)
//     ); 
// mac_reset_sync reset_ref_clk_sync(
//     .d_clk(ref_clk),
//     .rst_i(mac_reset_ref_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(mac_reset_ref_clk_in)
//     ); 
// mac_reset_sync mac_reset_ff_rx_clk_sync(
//     .d_clk(ff_clk),
//     .rst_i(mac_reset_ff_rx_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(mac_reset_ff_rx_clk_in)
//     ); 
// mac_reset_sync mac_reset_ff_tx_clk_sync(
//     .d_clk(ff_clk),
//     .rst_i(mac_reset_ff_tx_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(mac_reset_ff_tx_clk_in)
//     ); 
// mac_reset_sync xlaui_reset_rx_clk0_sync(
//     .d_clk(sd0_rx_clk),
//     .rst_i(xlaui_reset_rx_clk_temp[0]),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_rx_clk_in[0])
//     ); 
// mac_reset_sync xlaui_reset_rx_clk1_sync(
//     .d_clk(sd1_rx_clk),
//     .rst_i(xlaui_reset_rx_clk_temp[1]),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_rx_clk_in[1])
//     ); 
// mac_reset_sync xlaui_reset_rx_clk2_sync(
//     .d_clk(sd2_rx_clk),
//     .rst_i(xlaui_reset_rx_clk_temp[2]),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_rx_clk_in[2])
//     ); 
// mac_reset_sync xlaui_reset_rx_clk3_sync(
//     .d_clk(sd3_rx_clk),
//     .rst_i(xlaui_reset_rx_clk_temp[3]),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_rx_clk_in[3])
//     ); 
// mac_reset_sync xlaui_reset_tx_clk_sync(
//     .d_clk(sd_tx_clk),
//     .rst_i(xlaui_reset_tx_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_tx_clk_in)
//     ); 
// mac_reset_sync xlaui_reset_ref_clk_sync(
//     .d_clk(ref_clk),
//     .rst_i(xlaui_reset_ref_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(xlaui_reset_ref_clk_in)
//     ); 
// mac_reset_sync xaui_reset_rx_clk0_sync(
//     .d_clk(sd0_rx_clk),
//     .rst_i(xaui_reset_rx_clk_temp[0]),
//     .scan_mode(scan_mode),
//     .rst_o(xaui_reset_rx_clk_in[0])
//     ); 
// mac_reset_sync xaui_reset_rx_clk1_sync(
//     .d_clk(sd1_rx_clk),
//     .rst_i(xaui_reset_rx_clk_temp[1]),
//     .scan_mode(scan_mode),
//     .rst_o(xaui_reset_rx_clk_in[1])
//     ); 
// mac_reset_sync xaui_reset_rx_clk2_sync(
//     .d_clk(sd2_rx_clk),
//     .rst_i(xaui_reset_rx_clk_temp[2]),
//     .scan_mode(scan_mode),
//     .rst_o(xaui_reset_rx_clk_in[2])
//     ); 
// mac_reset_sync xaui_reset_rx_clk3_sync(
//     .d_clk(sd3_rx_clk),
//     .rst_i(xaui_reset_rx_clk_temp[3]),
//     .scan_mode(scan_mode),
//     .rst_o(xaui_reset_rx_clk_in[3])
//     ); 
// mac_reset_sync xaui_reset_tx_clk_sync(
//     .d_clk(sd_tx_clk),
//     .rst_i(xaui_reset_tx_clk_temp),
//     .scan_mode(scan_mode),
//     .rst_o(xaui_reset_tx_clk_in)
//     ); 


//*********************
//MAIN CORE
//*********************

// DFT port
// assign reset_reg_clk_temp       = scan_mode ? mac_reset      : (mac_reset      | reset_reg_clk      );
// assign mac_reset_ref_clk_temp   = scan_mode ? mac_reset      : (mac_reset      | mac_reset_ref_clk  );
// assign mac_reset_ff_rx_clk_temp = scan_mode ? mac_reset      : (mac_reset      | mac_reset_ff_rx_clk);
// assign mac_reset_ff_tx_clk_temp = scan_mode ? mac_reset      : (mac_reset      | mac_reset_ff_tx_clk);
// assign xlaui_reset_rx_clk_temp  = scan_mode ? {4{mac_reset}} : ({4{mac_reset}} | xlaui_reset_rx_clk );
// assign xlaui_reset_tx_clk_temp  = scan_mode ? mac_reset      : (mac_reset      | xlaui_reset_tx_clk );
// assign xlaui_reset_ref_clk_temp = scan_mode ? mac_reset      : (mac_reset      | xlaui_reset_ref_clk);
// assign xaui_reset_rx_clk_temp   = scan_mode ? {4{mac_reset}} : ({4{mac_reset}} | xaui_reset_rx_clk  );
// assign xaui_reset_tx_clk_temp   = scan_mode ? mac_reset      : (mac_reset      | xaui_reset_tx_clk  );

assign reset_reg_clk_temp       = mac_reset      | reset_reg_clk       ;
assign mac_reset_ref_clk_temp   = mac_reset      | mac_reset_ref_clk   ;
assign mac_reset_ff_rx_clk_temp = mac_reset      | mac_reset_ff_rx_clk ;
assign mac_reset_ff_tx_clk_temp = mac_reset      | mac_reset_ff_tx_clk ;
assign xlaui_reset_rx_clk_temp  = {4{mac_reset}} | xlaui_reset_rx_clk  ;
assign xlaui_reset_tx_clk_temp  = mac_reset      | xlaui_reset_tx_clk  ;
assign xlaui_reset_ref_clk_temp = mac_reset      | xlaui_reset_ref_clk ;
assign xaui_reset_rx_clk_temp   = {4{mac_reset}} | xaui_reset_rx_clk   ;
assign xaui_reset_tx_clk_temp   = mac_reset      | xaui_reset_tx_clk   ;

//clk_rdy
assign clk_rdy = (lane_40Geth_ena)? 1'd1 : mpllb_state;
//phy_config
assign bs_rx_bigswing_in      =     (bs_ce)? bs_rx_bigswing : 1'd1    ; 
assign bs_tx_lowswing_in      =     (bs_ce)? bs_tx_lowswing : 1'd0    ; 
assign mplla_bandwidth        =     11'd111 ; 
assign mplla_div10_clk_en     =     1'd1    ; 
assign mplla_div16p5_clk_en   =     1'd1    ; 
assign mplla_div8_clk_en      =     1'd0    ; 
assign mplla_div_clk_en       =     1'b0    ; 
assign mplla_div_multiplier   =     7'd10   ; 
assign mplla_force_en         =     1'd0    ; 
assign mplla_fracn_ctrl       =     9'd0    ; 
assign mplla_init_cal_disable =     1'd0    ; 
assign mplla_multiplier       =     8'd33   ; 
assign mplla_ssc_clk_sel      =     3'd0    ; 
assign mplla_ssc_en           =     1'd0    ; 
assign mplla_ssc_range        =     3'd0    ;
assign mpllb_bandwidth        =     11'd122 ; 
assign mpllb_div10_clk_en     =     1'd1    ; 
assign mpllb_div8_clk_en      =     1'd0    ; 
assign mpllb_div_clk_en       =     1'd0    ; 
assign mpllb_div_multiplier   =     7'd0    ; 
assign mpllb_force_en         =     1'd0    ; 
assign mpllb_fracn_ctrl       =     9'd0    ; 
assign mpllb_init_cal_disable =     1'd0    ; 
assign mpllb_multiplier       =     8'd40   ; 
assign mpllb_ssc_clk_sel      =     3'd0    ; 
assign mpllb_ssc_en           =     1'd0    ; 
assign mpllb_ssc_range        =     3'd0    ; 

assign ref_clk_div2_en        =     1'd0    ; 
assign ref_clk_mplla_div2_en  =     1'd1    ; 
assign ref_clk_mpllb_div2_en  =     1'd1    ; 
assign ref_range              =     3'd6    ; 
assign rxx_adapt_afe_en       =     (lane_40Geth_ena)? 1'd1:1'd0; 
assign rxx_adapt_cont         =     1'd1    ; //?
assign rxx_adapt_dfe_en       =     (lane_40Geth_ena)? 1'd1:1'd0; 
assign rxx_adapt_req          =     1'd0    ; 
assign rxx_align_en           =     1'd0    ; //??
assign rxx_cdr_ssc_en         =     1'd0    ; 
assign rxx_cdr_track_en       =     1'd1    ; 
assign rxx_cdr_vco_lowfreq    =     1'd1    ; 
assign rxx_clk_shift          =     1'd0    ; 
assign rxx_data_en            =     1'd1    ; 
assign rxx_disable            =     1'd0    ; 
assign rxx_div16p5_clk_en     =     (lane_40Geth_ena)? 1'd1:1'd0; 
assign rxx_eq_att_lvl         =     3'd0    ; 
assign rxx_eq_ctle_boost      =     (lane_40Geth_ena)? 5'd10:5'd6; 
assign rxx_eq_ctle_pole       =     (lane_40Geth_ena)? 3'd2:3'd0; 
assign rxx_eq_dfe_tap1        =     8'd0    ; 
assign rxx_eq_vga1_gain       =     4'd7    ; 
assign rxx_eq_vga2_gain       =     4'd7    ; 
assign rxx_invert             =     1'd0    ; 
assign rxx_los_lfps_en        =     1'd0    ; 
assign rxx_los_threshold      =     3'd6    ; 
assign rxx_lpd                =     1'd0    ; 
assign rxx_offcan_cont        =     1'd1    ; 
assign rxx_pstate             =     2'd0    ; 
assign rxx_rate               =     (lane_40Geth_ena)? 2'd0:2'd2; 
assign rxx_ref_ld_val         =     (lane_40Geth_ena)? 6'd41:6'd34; 
assign rxx_term_acdc          =     1'd1    ; 
assign rxx_term_en            =     1'd1    ; 
assign rxx_vco_ld_val         =     (lane_40Geth_ena)? 13'd1353:13'd1360; 
assign rxx_width              =     2'd3; 
assign txx_beacon_en          =     1'd0    ; 
assign txx_data_en            =     1'd1    ; 
assign txx_detrx_req          =     1'd0    ; 
assign txx_disable            =     1'd0    ; 
assign txx_eq_main            =     (lane_40Geth_ena)? 6'd40:6'd32; 
assign txx_eq_post            =     (lane_40Geth_ena)? 6'd0:6'd32; 
assign txx_eq_pre             =     (lane_40Geth_ena)? 6'd0:6'd0; 
assign txx_iboost_lvl         =     4'd15   ; 
assign txx_invert             =     1'd0    ; 
assign txx_lpd                =     1'd0    ; 
assign txx_mpll_en            =     1'd1    ; 
assign txx_mpllb_sel          =     (lane_40Geth_ena)? 1'd0:1'd1; 
assign txx_pstate             =     2'd0    ; 
assign txx_rate               =     (lane_40Geth_ena)? 2'd0:2'd2; 
assign txx_vboost_en          =     1'd1; 
assign txx_width              =     2'd3; 
assign tx_vboost_lvl          =     3'd5    ; 
assign rx_vref_ctrl           =     5'd15   ; 


assign tx0_clk_rdy = (pcs_40Geth_ena)? mplla_state:mpllb_state;
assign tx1_clk_rdy = (pcs_40Geth_ena)? mplla_state:mpllb_state;
assign tx2_clk_rdy = (pcs_40Geth_ena)? mplla_state:mpllb_state;
assign tx3_clk_rdy = (pcs_40Geth_ena)? mplla_state:mpllb_state;

assign tx0_master_mplla_state = mplla_state;
assign tx0_master_mpllb_state = mpllb_state;

assign tx1_master_mplla_state = mplla_state;
assign tx1_master_mpllb_state = mpllb_state;

assign tx2_master_mplla_state = mplla_state;
assign tx2_master_mpllb_state = mpllb_state;

assign tx3_master_mplla_state = mplla_state;
assign tx3_master_mpllb_state = mpllb_state;


// always @(posedge sd0_rx_clk) begin
//     rx0_data_dl <= rx0_data;
// end
// always @(posedge sd1_rx_clk) begin
//     rx1_data_dl <= rx1_data;
// end
// always @(posedge sd2_rx_clk) begin
//     rx2_data_dl <= rx2_data;
// end
// always @(posedge sd3_rx_clk) begin
//     rx3_data_dl <= rx3_data;
// end

genvar i;
generate for(i = 0; i < 20; i = i+1)
begin:sd_link
    assign sd0_rx[i] = (sd_tx2rx_par_lb_en)? 
                        sd0_tx[i] : ((rx0_valid & (~mac_reset)) ? 
                        rx0_data[19-i] : 1'b0);
    assign sd1_rx[i] = (sd_tx2rx_par_lb_en)? 
                        sd1_tx[i] : ((rx1_valid & (~mac_reset)) ? 
                        rx1_data[19-i] : 1'b0);
    assign sd2_rx[i] = (sd_tx2rx_par_lb_en)? 
                        sd2_tx[i] : ((rx2_valid & (~mac_reset)) ? 
                        rx2_data[19-i] : 1'b0);
    assign sd3_rx[i] = (sd_tx2rx_par_lb_en)? 
                        sd3_tx[i] : ((rx3_valid & (~mac_reset)) ? 
                        rx3_data[19-i] : 1'b0);
    assign tx0_data[19-i] = (sd_tx2rx_par_lb_en)? 1'b0 : sd0_tx[i];
    assign tx1_data[19-i] = (sd_tx2rx_par_lb_en)? 1'b0 : sd1_tx[i];
    assign tx2_data[19-i] = (sd_tx2rx_par_lb_en)? 1'b0 : sd2_tx[i];
    assign tx3_data[19-i] = (sd_tx2rx_par_lb_en)? 1'b0 : sd3_tx[i];
end
endgenerate

    assign signal_det0 = rx0_valid;
    assign signal_det1 = rx1_valid;
    assign signal_det2 = rx2_valid;
    assign signal_det3 = rx3_valid;

endmodule


// module mac_reset_sync
// (
//   input  wire d_clk,
//   input  wire rst_i,
//   input  wire scan_mode,// DFT port
//   output wire rst_o
// );
//   reg rst_o_temp;
//   reg rst_o_temp1;
//   reg rst_o_temp2;

//   always @(posedge d_clk or posedge rst_i) begin
//     if (rst_i) begin
//        rst_o_temp     <= 1'b1;
//        rst_o_temp1    <= 1'b1;
//        rst_o_temp2    <= 1'b1;   
//     end
//     else begin
//        rst_o_temp     <= 1'b0;
//        rst_o_temp1    <= rst_o_temp;
//        rst_o_temp2    <= rst_o_temp1;
//     end
//   end

//   assign rst_o = scan_mode ? rst_i : rst_o_temp2 ;
// endmodule

module hdfwd_rstp_sync(
  output SyncOut,
  input CLK,
  input SET,
  input ARST_bypass,
  input testmode,
  input SyncIn );

  wire Sync2;
  wire nSET;
  assign nSET = ~SET;

  SDFFYSQ2D_X2M_A12PP140ZTS_C35 
    xd_rstp_sync2 (.Q(Sync2), .CK(CLK), .D(SyncIn), .SN(nSET), .SE(1'b0), .SI(1'b0));

  assign SyncOut = testmode ? ARST_bypass : Sync2;
endmodule

module hdfwd_rstn_sync(
  output SyncOut,
  input CLK,
  input nRESET,
  input nRESET_bypass,
  input testmode,
  input SyncIn );

  wire Sync2;
  wire ARST;
  assign ARST = ~nRESET;

  SDFFYRPQ2D_X2M_A12PP140ZTS_C35
    xd_rstn_sync2 (.Q(Sync2), .CK(CLK), .D(SyncIn), .R(ARST), .SE(1'b0), .SI(1'b0));

  assign SyncOut = testmode ? nRESET_bypass : Sync2;
endmodule
